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2006 Microchip Technology Inc.
Advance Information
DS39758B-page 299
PIC18F1230/1330
INDEX
A
A/D ...................................................................................164
A/D Converter Interrupt, Configuring .......................168
Acquisition Requirements ........................................169
ADCON0 Register ....................................................164
ADCON1 Register ....................................................164
ADCON2 Register ....................................................164
ADRESH Register ............................................164, 167
ADRESL Register ....................................................164
Analog Port Pins, Configuring ..................................171
Associated Registers ...............................................173
Configuring the Module ............................................168
Conversion Clock (T
AD
) ...........................................170
Conversion Requirements .......................................286
Conversion Status (GO/DONE Bit) ..........................167
Conversions .............................................................172
Converter Characteristics ........................................285
Discharge .................................................................172
Operation in Power-Managed Modes ......................171
Selecting and Configuring Acquisition Time ............170
Triggering Conversions ............................................169
Absolute Maximum Ratings .............................................258
AC (Timing) Characteristics .............................................277
Conditions ................................................................278
Load Conditions for Device
Timing Specifications .......................................278
Parameter Symbology .............................................277
Temperature and Voltage Specifications .................278
AC Characteristics
Internal RC Accuracy ...............................................280
Access Bank
Mapping with Indexed Literal Offset
Addressing Mode ...............................................63
Remapping with Indexed Literal Offset
Addressing Mode ...............................................63
ADCON0 Register ............................................................164
GO/DONE Bit ...........................................................167
ADCON1 Register ............................................................164
ADCON2 Register ............................................................164
ADDFSR ..........................................................................251
ADDLW ............................................................................214
ADDULNK ........................................................................251
ADDWF ............................................................................214
ADDWFC .........................................................................215
ADRESH Register ............................................................164
ADRESL Register ....................................................164, 167
Analog-to-Digital Converter. See A/D.
ANDLW ............................................................................215
ANDWF ............................................................................216
Assembler
MPASM Assembler ..................................................205
B
BC ....................................................................................216
BCF ..................................................................................217
Block Diagrams
A/D ...........................................................................167
Analog Input Model ..................................................168
Comparator Analog Input Model ..............................176
Comparator Voltage Reference ...............................179
Dead-Time Control Unit for
One PWM Output Pair .....................................129
Device Clock .............................................................. 20
EUSART Receive .................................................... 154
EUSART Transmit ................................................... 152
External Power-on Reset Circuit
(Slow V
DD
Power-up) ........................................ 35
Fail-Safe Clock Monitor ........................................... 198
Generic I/O Port ......................................................... 81
Interrupt Logic ............................................................ 88
Low-Voltage Detect ................................................. 181
On-Chip Reset Circuit ................................................ 33
PIC18F1230/1330 ..................................................... 10
PLL (HS Mode) .......................................................... 17
Power Control PWM ................................................ 112
PWM (One Output Pair,
Complementary Mode) .................................... 113
PWM (One Output Pair,
Independent Mode) ......................................... 113
PWM I/O Pin ............................................................ 136
PWM Time Base ...................................................... 115
Reads from Flash Program Memory ......................... 69
Single Comparator ................................................... 175
Table Read Operation ............................................... 65
Table Write Operation ............................................... 66
Table Writes to Flash Program Memory .................... 71
Timer0 in 16-Bit Mode ............................................. 102
Timer0 in 8-Bit Mode ............................................... 102
Timer1 ..................................................................... 106
Timer1 (16-Bit Read/Write Mode) ............................ 106
Watchdog Timer ...................................................... 195
BN .................................................................................... 217
BNC ................................................................................. 218
BNN ................................................................................. 218
BNOV .............................................................................. 219
BNZ ................................................................................. 219
BOR. See Brown-out Reset.
BOV ................................................................................. 222
BRA ................................................................................. 220
Brown-out Reset (BOR) ..................................................... 36
Detecting ................................................................... 36
Disabling in Sleep Mode ............................................ 36
Software Enabled ...................................................... 36
BSF .................................................................................. 220
BTFSC ............................................................................. 221
BTFSS ............................................................................. 221
BTG ................................................................................. 222
BZ .................................................................................... 223
C
C Compilers
MPLAB C18 ............................................................. 205
MPLAB C30 ............................................................. 205
CALL ................................................................................ 223
CALLW ............................................................................ 252
Clock Sources .................................................................... 20
Selecting the 31 kHz Source ..................................... 21
Selection Using OSCCON Register .......................... 21
CLRF ............................................................................... 224
CLRWDT ......................................................................... 224