PIC18F1230/1330
DS39758B-page 112
Advance Information
2006 Microchip Technology Inc.
FIGURE 13-1:
POWER CONTROL PWM MODULE BLOCK DIAGRAM
PDC2
PDC2 Buffer
Output
Driver
Block
PWMCON0
PTPER Buffer
PWMCON1
PTPER
PTMR
Comparator
Comparator
Channel 2
PTCONx
SEVTCMP
Comparator
Special Event Trigger
OVDCON<D/S>
PWM Enable and Mode
PWM Manual Control
PWM
PWM
PWM Generator #2
(1)
SEVTDIR
PTDIR
DTCON
Dead-Time Control
Special Event
Postscaler
FLTA
PWM0
PWM1
PWM2
PWM3
Note 1:
Only PWM Generator 2 is shown in detail. The other generators are identical; their details are omitted for clarity.
PWM4
PWM5
FLTCONFIG
Fault Pin Control
Dead-Time Generator
and Override Logic
(1)
Channel 1
Dead-Time Generator
and Override Logic
Channel 0
Dead-Time Generator
and Override Logic
Internal Data Bus
8
8
8
8
8
8
8
8
8
8
Generator 0
Generator 1
