參數(shù)資料
型號: PIC16LF84A
廠商: Microchip Technology Inc.
英文描述: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
中文描述: 18引腳增強型閃存/ EEPROM的8位微控制器
文件頁數(shù): 29/68頁
文件大小: 494K
代理商: PIC16LF84A
PIC16F84A
1998 Microchip Technology Inc.
Preliminary
DS35007A-page 29
6.8.1
INT INTERRUPT
External interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION_REG<6>) is set,
or falling, if INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing control bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software via the interrupt service
routine before re-enabling this interrupt. The INT
interrupt can wake the processor from SLEEP
(Section 6.11) only if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether
the processor branches to the interrupt vector
following wake-up.
6.8.2
TMR0 INTERRUPT
An overflow (FFh
00h) in TMR0 will set flag bit T0IF
(INTCON<2>). The interrupt can be enabled/disabled
by setting/clearing enable bit T0IE (INTCON<5>)
(Section 4.0).
6.8.3
PORB INTERRUPT
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<3>)
(Section 3.2).
6.8.4
DATA EEPROM INTERRUPT
At the completion of a data EEPROM write cycle, flag
bit EEIF (EECON1<4>) will be set. The interrupt can be
enabled/disabled by setting/clearing enable bit EEIE
(INTCON<6>) (Section 5.0).
6.9
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users wish to save key register
values during an interrupt (e.g., W register and STATUS
register). This is implemented in software.
Example 6-1 stores and restores the STATUS and W
register’s values. The User defined registers, W_TEMP
and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
Example 6-1 does the following:
a)
Stores the W register.
b)
Stores the STATUS register in STATUS_TEMP.
c)
Executes the Interrupt Service Routine code.
d)
Restores the STATUS (and bank select bit)
register.
e)
Restores the W register.
EXAMPLE 6-1:
SAVING STATUS AND W REGISTERS IN RAM
PUSH MOVWF W_TEMP ; Copy W to TEMP register,
SWAPF STATUS, W ; Swap status to be saved into W
MOVWF STATUS_TEMP ; Save status to STATUS_TEMP register
ISR : :
: ; Interrupt Service Routine
: ; should configure Bank as required
: ;
POP SWAPF STATUS_TEMP, W ; Swap nibbles in STATUS_TEMP register
; and place result into W
MOVWF STATUS ; Move W into STATUS register
; (sets bank to original state)
SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMP
SWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W
Note 1:
For a change on the I/O pin to be
recognized, the pulse width must be at
least T
CY
wide.
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