參數資料
型號: PIC16LF84A
廠商: Microchip Technology Inc.
英文描述: 18-pin Enhanced Flash/EEPROM 8-Bit Microcontroller
中文描述: 18引腳增強型閃存/ EEPROM的8位微控制器
文件頁數: 19/68頁
文件大?。?/td> 494K
代理商: PIC16LF84A
PIC16F84A
1998 Microchip Technology Inc.
Preliminary
DS35007A-page 19
5.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full V
DD
range). This memory
is not directly mapped in the register file space. Instead
it is indirectly addressed through the Special Function
Registers. There are four SFRs used to read and write
this memory. These registers are:
EECON1
EECON2 (Not a physically implemented register)
EEDATA
EEADR
EEDATA holds the 8-bit data for read/write, and EEADR
holds the address of the EEPROM location being
accessed. PIC16F84A devices have 64 bytes of data
EEPROM with an address range from 0h to 3Fh.
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write-
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC specifications for
exact limits.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
The device programmer can no longer access
this memory.
Additional information on the Data EEPROM is avail-
able in the PICmicro Mid-Range Reference Manual,
(DS33023).
FIGURE 5-1:
EECON1 REGISTER (ADDRESS 88h)
U
bit7
U
U
R/W-0
EEIF
R/W-x
WRERR
R/W-0
WREN
R/S-0
WR
R/S-x
RD
R
W = Writable bit
S
= Settable bit
U
= Unimplemented bit,
read as ‘0’
- n = Value at POR reset
= Readable bit
bit0
bit 7:5
bit 4
Unimplemented:
Read as '0'
EEIF
: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
WRERR
: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
0 = The write operation completed
WREN
: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
WR
: Write Control bit
1 = initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit can only
be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
RD
: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit can only
be set (not cleared) in software).
0 = Does not initiate an EEPROM read
bit 3
bit 2
bit 1
bit 0
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