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參數(shù)資料
| 型號： | PIC16LCE625T-04I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 70/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 2K OTP W/EEPRM18SOIC |
| 標準包裝： | 1,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| EEPROM 大小： | 128 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16LCE625T04ISO |
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1999 Microchip Technology Inc.
DS40182C-page 61
PIC16CE62X
10.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key reg-
isters during an interrupt (i.e. W register and STATUS
register). This will have to be implemented in software.
Example 10-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x70 in Bank 0 and it must also be defined at 0xF0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 10-1:
Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
Restores the W register
EXAMPLE 10-1: SAVING THE STATUS AND
W REGISTERS IN RAM
MOVWF
W_TEMP
;copy W to temp register,
;could be in either bank
SWAPF
STATUS,W
;swap status to be saved into W
BCF
STATUS,RP0
;change to bank 0 regardless
;of current bank
MOVWF
STATUS_TEMP
;save status to bank 0
;register
:
(ISR)
:
SWAPF
STATUS_TEMP,W
;swap STATUS_TEMP register
;into W, sets bank to original
;state
MOVWF
STATUS
;move W into STATUS register
SWAPF
W_TEMP,F
;swap W_TEMP
SWAPF
W_TEMP,W
;swap W_TEMP into W
10.7
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscil-
lator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
have been stopped, for example, by execution of a
SLEEP
instruction. During normal operation, a WDT
time-out generates a device RESET. If the device is in
SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the con-
figuration bit WDTE as clear (Section 10.1).
10.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
10.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler), it may take several seconds before a
WDT time-out occurs.
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