參數(shù)資料
型號(hào): PIC16LCE625T-04I/SO
廠(chǎng)商: Microchip Technology
文件頁(yè)數(shù): 22/100頁(yè)
文件大?。?/td> 0K
描述: IC MCU CMOS 2K OTP W/EEPRM18SOIC
標(biāo)準(zhǔn)包裝: 1,100
系列: PIC® 16C
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 13
程序存儲(chǔ)器容量: 3.5KB(2K x 14)
程序存儲(chǔ)器類(lèi)型: OTP
EEPROM 大?。?/td> 128 x 8
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 18-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
其它名稱(chēng): PIC16LCE625T04ISO
PIC16CE62X
DS40182C-page 18
1999 Microchip Technology Inc.
4.2.2.4
PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
REGISTER 4-4:
PIE1 REGISTER (ADDRESS 8CH)
U-0
R/W-0
U-0
—CMIE
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit7
bit0
bit 7:
Unimplemented: Read as ’0’
bit 6:
CMIE: Comparator Interrupt Enable bit
1
= Enables the Comparator interrupt
0
= Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as ’0’
4.2.2.5
PIR1 REGISTER
This register contains the individual flag bit for the com-
parator interrupt.
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable
bit,
GIE
(INTCON<7>).
User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 4-5:
PIR1 REGISTER (ADDRESS 0CH)
U-0
R/W-0
U-0
—CMIF
R
= Readable bit
W = Writable bit
U
= Unimplemented bit,
read as ‘0’
-n = Value at POR reset
-x = Unknown at POR reset
bit7
bit0
bit 7:
Unimplemented: Read as ’0’
bit 6:
CMIF: Comparator Interrupt Flag bit
1
= Comparator input has changed
0
= Comparator input has not changed
bit 5-0: Unimplemented: Read as ’0’
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