- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3886 > PIC16LCE625T-04I/SO (Microchip Technology)IC MCU CMOS 2K OTP W/EEPRM18SOIC PDF資料下載
參數(shù)資料
| 型號： | PIC16LCE625T-04I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 52/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 2K OTP W/EEPRM18SOIC |
| 標準包裝： | 1,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| EEPROM 大小： | 128 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16LCE625T04ISO |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁
1999 Microchip Technology Inc.
DS40182C-page 45
PIC16CE62X
8.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of either comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<7:6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<6>, is the comparator interrupt flag.
The CMIF bit must be reset by clearing ‘0’. Since it is
also possible to write a '1' to this register, a simulated
interrupt may be initiated.
The
CMIE
bit
(PIE1<6>)
and
the
PEIE
bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are clear, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
The user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
Any read or write of CMCON. This will end the
mismatch condition.
b)
Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
8.7
Comparator Operation During SLEEP
When a comparator is active and the device is placed
in SLEEP mode, the comparator remains active and
the interrupt is functional if enabled. This interrupt will
Note:
If a change in the CMCON register
(C1OUT or C2OUT) should occur when a
read operation is being executed (start of
the Q2 cycle), then the CMIF (PIR1<6>)
interrupt flag may not get set.
wake-up the device from SLEEP mode when enabled.
While the comparator is powered-up, higher sleep
currents than shown in the power down current
specification will occur. Each comparator that is
operational will consume additional current as shown in
the comparator specifications. To minimize power
consumption while in SLEEP mode, turn off the
comparators, CM<2:0> = 111, before entering sleep. If
the device wakes-up from sleep, the contents of the
CMCON register are not affected.
8.8
Effects of a RESET
A device reset forces the CMCON register to its reset
state. This forces the comparator module to be in the
comparator reset mode, CM<2:0> = 000. This ensures
that all potential inputs are analog inputs. Device cur-
rent is minimized when analog inputs are present at
reset time. The comparators will be powered-down
during the reset interval.
8.9
Analog Input Connection
Considerations
A simplified circuit for an analog input is shown in
Figure 8-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latch-up may occur. A
maximum
source
impedance
of
10 k
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
FIGURE 8-4:
ANALOG INPUT MODEL
VA
RS < 10K
AIN
CPIN
5 pF
VDD
VT = 0.6V
RIC
ILEAKAGE
±500 nA
VSS
Legend
CPIN
= Input capacitance
VT
= Threshold voltage
ILEAKAGE
= Leakage current at the pin due to various junctions
RIC
= Interconnect resistance
RS
= Source impedance
VA
= Analog voltage
相關PDF資料 |
PDF描述 |
|---|---|
| 2-84981-8 | CONN FFC 28POS 1.00MM R/A SMD |
| 2-84981-7 | CONN FFC 27POS 1.00MM R/A SMD |
| 2-84981-6 | CONN FFC 26POS 1.00MM R/A SMD |
| 2-84981-5 | CONN FFC 25POS 1.00MM R/A SMD |
| 2-84981-4 | CONN FFC 24POS 1.00MM R/A SMD |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PIC16LF1454-E/ML | 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 7KB FLASH 16QFN 制造商:Microchip Technology Inc 功能描述:8-bit Microcontrollers - MCU 7KB Flsh 512b RAM 48MHz Int Osc 12 I/0 |
| PIC16LF1454-E/P | 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 7KB FLASH 14PDIP |
| PIC16LF1454-E/SL | 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:7 KB Flash, 512 bytes RAM, 48 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, USB 2.0, NanoWatt XLP |
| PIC16LF1454-E/ST | 制造商:Microchip Technology Inc 功能描述:7 KB FLASH, 512 BYTES RAM, 48 MHZ INT. OSC, 12 I/0, ENHANCED - Rail/Tube 制造商:Microchip Technology Inc 功能描述:IC MCU 8BIT 7KB FLASH 14TSSOP |
| PIC16LF1454-I/ML | 功能描述:8位微控制器 -MCU 7 KB Flash 512 bytes RAM 48 MHz Int Osc RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。