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參數(shù)資料
| 型號： | PIC16LCE625T-04I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 63/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU CMOS 2K OTP W/EEPRM18SOIC |
| 標準包裝： | 1,100 |
| 系列： | PIC® 16C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 外圍設備： | 欠壓檢測/復位，POR，WDT |
| 輸入/輸出數(shù)： | 13 |
| 程序存儲器容量： | 3.5KB（2K x 14） |
| 程序存儲器類型： | OTP |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 128 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | PIC16LCE625T04ISO |
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1999 Microchip Technology Inc.
DS40182C-page 55
PIC16CE62X
10.4.5
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired, then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 10-8,
Figure 10-9
and
Figure 10-10
depict
time-out
sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 10-9). This is useful for testing purposes or
to synchronize more than one PICmicro device oper-
ating in parallel.
Table 10-5 shows the reset conditions for some special
registers, while Table 10-6 shows the reset conditions
for all the registers.
10.4.6
POWER CONTROL (PCON)/STATUS
REGISTER
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BOR (Brown-out). BOR is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BOR = 0
indicating that a brown-out has occurred. The BOR
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BODEN bit = 0 in the Configuration word).
Bit1
is
POR
(Power-on-reset).
It
is
a
‘0’
on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subsequent reset, if POR is ‘0’, it will indicate that
a power-on-reset must have occurred (VDD may have
gone too low).
TABLE 10-3:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 10-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
Legend: x = unknown, u = unchanged
Oscillator Configuration
Power-up
Brown-out Reset
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 TOSC
1024 TOSC
72 ms + 1024 TOSC
1024 TOSC
RC
72 ms
—
72 ms
—
POR
BOR
TO
PD
0X11
Power-on-reset
0X0X
Illegal, TO is set on POR
0XX0
Illegal, PD is set on POR
10XX
Brown-out Reset
110u
WDT Reset
1100
WDT Wake-up
11uu
MCLR reset during normal operation
1110
MCLR reset during SLEEP
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