參數(shù)資料
型號: PIC16LC716T
廠商: Microchip Technology Inc.
英文描述: 8-Bit CMOS Microcontrollers with A/D Converter and Capture/Compare/PWM
中文描述: 8位CMOS微控制器與A / D轉(zhuǎn)換器和捕捉/比較/ PWM
文件頁數(shù): 63/108頁
文件大?。?/td> 1810K
代理商: PIC16LC716T
1999 Microchip Technology Inc.
Preliminary
DS41106A-page 63
PIC16C712/716
9.12
Watchdog Timer (WDT)
The Watchdog Timer is as a free running, on-chip, RC
oscillator which does not require any external compo-
nents. This RC oscillator is separate from the RC oscil-
lator of the OSC1/CLKIN pin. That means that the WDT
will run, even if the clock on the OSC1/CLKIN and
OSC2/CLKOUT pins of the device have been stopped,
for example, by execution of a
SLEEP
instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the STATUS register
will be cleared upon a Watchdog Timer time-out.
The WDT can be permanently disabled by clearing
configuration bit WDTE (Section 9.1).
WDT time-out period values may be found in the Elec-
trical Specifications section under T
WDT
(parameter
#31). Values for the WDT prescaler (actually a
postscaler, but shared with the Timer0 prescaler) may
be assigned using the OPTION_REG register.
.
Note:
The
CLRWDT
and
SLEEP
instructions clear
the WDT and the postscaler, if assigned to
the WDT, and prevent it from timing out and
generating a device RESET condition.
Note:
When a
CLRWDT
instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but the
prescaler assignment is not changed.
FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM
FIGURE 9-16: SUMMARY OF WATCHDOG TIMER REGISTERS
Address Name
Bits 13:8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2007h
81h
Legend: Shaded cells are not used by the Watchdog Timer.
Note1:
See Figure 9-1 for operation of these bits.
Config. bits
(1)
N/A
BODEN
(1)
INTEDG
CP1
T0CS T0SE
CP0
PWRTE
(1)
PSA
WDTE
PS2
FOSC1
PS1
FOSC0
PS0
OPTION_REG
RBPU
From TMR0 Clock Source
(Figure 4-2)
To TMR0 (Figure 4-2)
Postscaler
WDT Timer
WDT
Enable Bit
0
1
M
U
X
PSA
8 - to - 1 MUX
PS2:PS0
0
1
MUX
PSA
WDT
Time-out
Note:
PSA and PS2:PS0 are bits in the OPTION_REG register.
8
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