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1999 Microchip Technology Inc.
Preliminary
DS41106A-page 101
PIC16C712/716
INDEX
A
A/D .....................................................................................45
A/D Converter Enable (ADIE Bit) ...............................16
A/D Converter Flag (ADIF Bit) .............................17, 47
A/D Converter Interrupt, Configuring .........................47
ADCON0 Register ................................................11, 45
ADCON1 Register ..........................................12, 45, 46
ADRES Register ............................................11, 45, 47
Analog Port Pins, Configuring ....................................49
Block Diagram ............................................................47
Block Diagram, Analog Input Model ...........................48
Channel Select (CHS2:CHS0 Bits) ............................45
Clock Select (ADCS1:ADCS0 Bits) ............................45
Configuring the Module ..............................................47
Conversion Clock (T
AD
) .............................................49
Conversion Status (GO/DONE Bit) ......................45, 47
Conversions ...............................................................50
Converter Characteristics ..........................................88
Module On/Off (ADON Bit) .........................................45
Port Configuration Control (PCFG2:PCFG0 Bits) ......46
Sampling Requirements .............................................48
Special Event Trigger (CCP) ................................41, 50
Timing Diagram ..........................................................89
Absolute Maximum Ratings ...............................................75
ADCON0 Register ........................................................11, 45
ADCS1:ADCS0 Bits ...................................................45
ADON Bit ...................................................................45
CHS2:CHS0 Bits ........................................................45
GO/DONE Bit .......................................................45, 47
ADCON1 Register ..................................................12, 45, 46
PCFG2:PCFG0 Bits ...................................................46
ADRES Register ....................................................11, 45, 47
Architecture
PIC16C62B/PIC16C72A Block Diagram ......................5
Assembler
MPASM Assembler ....................................................71
B
Banking, Data Memory ................................................10, 13
Brown-Out Detect (BOD) ...................................................55
Brown-out Reset (BOR) ...................................51, 54, 58, 59
BOR Enable (BODEN Bit) ..........................................52
BOR Status (BOR Bit) ................................................18
Timing Diagram ..........................................................85
C
Capture (CCP Module) ......................................................40
Block Diagram ............................................................40
CCP Pin Configuration ...............................................40
CCPR1H:CCPR1L Registers .....................................40
Changing Between Capture Prescalers .....................40
Software Interrupt ......................................................40
Timer1 Mode Selection ..............................................40
Capture/Compare/PWM (CCP) ..........................................39
CCP1CON Register .............................................11, 39
CCPR1H Register ................................................11, 39
CCPR1L Register ................................................11, 39
Enable (CCP1IE Bit) ..................................................16
Flag (CCP1IF Bit) .......................................................17
Timer Resources ........................................................39
Timing Diagram ..........................................................87
CCP1CON Register ...........................................................39
CCP1M3:CCP1M0 Bits ..............................................39
CCP1X:CCP1Y Bits ...................................................39
Code Protection ........................................................... 51, 65
CP1:CP0 Bits ............................................................. 52
Compare (CCP Module) .................................................... 41
Block Diagram ........................................................... 41
CCP Pin Configuration .............................................. 41
CCPR1H:CCPR1L Registers .................................... 41
Software Interrupt ...................................................... 41
Special Event Trigger .................................... 34, 41, 50
Timer1 Mode Selection .............................................. 41
Configuration Bits .............................................................. 51
Conversion Considerations ................................................ 99
D
Data Memory ..................................................................... 10
Bank Select (RP1:RP0 Bits) ................................ 10, 13
General Purpose Registers ....................................... 10
Register File Map ...................................................... 10
Special Function Registers ........................................ 11
DC Characteristics ....................................................... 77, 79
Development Support ........................................................ 69
Development Tools ............................................................ 69
Direct Addressing .............................................................. 20
E
Electrical Characteristics ................................................... 75
Errata ................................................................................... 3
External Power-on Reset Circuit ........................................ 55
F
Family of Devices
PIC16C7XX ................................................................. 2
Firmware Instructions ........................................................ 67
Fuzzy Logic Dev. System (fuzzyTECH
-MP) ................... 71
I
I/O Ports ............................................................................ 21
ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 69
ID Locations ................................................................. 51, 65
In-Circuit Serial Programming (ICSP) .......................... 51, 65
Indirect Addressing ............................................................ 20
FSR Register ................................................. 10, 11, 20
INDF Register ............................................................ 11
Instruction Format .............................................................. 67
Instruction Set .................................................................... 67
Summary Table ......................................................... 68
INTCON Register ......................................................... 11, 15
GIE Bit ....................................................................... 15
INTE Bit ..................................................................... 15
INTF Bit ..................................................................... 15
PEIE Bit ..................................................................... 15
RBIE Bit ..................................................................... 15
RBIF Bit ............................................................... 15, 24
T0IE Bit ...................................................................... 15
T0IF Bit ...................................................................... 15
Interrupt Sources ......................................................... 51, 61
A/D Conversion Complete ......................................... 47
Block Diagram ........................................................... 61
Capture Complete (CCP) .......................................... 40
Compare Complete (CCP) ........................................ 41
Interrupt on Change (RB7:RB4 ) ............................... 24
RB0/INT Pin, External ............................................... 62
TMR0 Overflow .................................................... 30, 62
TMR1 Overflow .................................................... 31, 34
TMR2 to PR2 Match .................................................. 37
TMR2 to PR2 Match (PWM) ................................ 36, 42
Interrupts, Context Saving During ...................................... 62
Interrupts, Enable Bits