參數(shù)資料
型號： PIC16F819
廠商： Microchip Technology Inc.
英文描述： 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology(18/20引腳，納瓦技術(shù)增強FLASH微控制器)
中文描述： 18/20-Pin增強型閃存微控制器采用納瓦技術(shù)（18/20引腳，納瓦技術(shù)增強閃存微控制器）
文件頁數(shù)： 81/164頁
文件大?。?/td> 3045K
代理商： PIC16F819
2002 Microchip Technology Inc.
Preliminary
DS39598C-page 79
PIC16F818/819
10.3.2
MASTER MODE OPERATION
Master mode operation is supported in firmware using
interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a RESET, or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I
2
C bus may be taken when the P bit is set, or the
bus is IDLE and both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low, irre-
spective of the value(s) in PORTB<4,1>. So when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I
2
C module.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
START condition
STOP condition
Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 =
1011
), or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Master mode operation, see
AN554, “Software Implementation of I
2
C Bus Master”
.
10.3.3
MULTI-MASTER MODE OPERATION
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the START and STOP condi-
tions allows the determination of when the bus is free.
The STOP (P) and START (S) bits are cleared from a
RESET, or when the SSP module is disabled. The
STOP (P) and START (S) bits will toggle based on the
START and STOP conditions. Control of the I
2
C bus
may be taken when bit P (SSPSTAT<4>) is set, or the
bus is IDLE and both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the STOP condition occurs.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected out-
put level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB<4,1>). There are two stages
where this arbitration can be lost:
Address Transfer
Data Transfer
When the slave logic is enabled, the Slave device con-
tinues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data trans-
fer stage, the device will need to re-transfer the data at
a later time.
For more information on Multi-Master mode operation,
see
AN578, “Use of the SSP Module in the of I
2
C
Multi-Master Environment”
.
TABLE 10-3:
REGISTERS ASSOCIATED WITH I
2
C OPERATION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh,
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF TMR2IF TMR1IF
-0-- 0000
-0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE CCP1IE TMR2IE TMR1IE
-0-- 0000
-0-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD
Synchronous Serial Port (I
2
C mode) Address Register
0000 0000
0000 0000
14h
SSPCON
WCOL
SSPOV
SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0
0000 0000
0000 0000
94h
SSPSTAT
SMP
(1)
CKE
(1)
D/A
P
S
R/W
UA
BF
0000 0000
0000 0000
86h
TRISB
PORTB Data Direction register
1111 1111
1111 1111
Legend:
x
= unknown,
u
= unchanged,
-
= unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI mode.
Note 1:
Maintain these bits clear in I
2
C mode.
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參數(shù)描述
PIC16F819-E/ML 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F819-E/P 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F819-E/SO 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F819-E/SS 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F819-E/SSVAO 制造商:Microchip Technology Inc 功能描述:
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