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2002 Microchip Technology Inc.
Preliminary
DS39598C-page 157
PIC16F818/819
T
T1CKPS0 Bit
......................................................................57
T1CKPS1 Bit
......................................................................57
T1OSCEN Bit
.....................................................................57
T1SYNC Bit
........................................................................57
T2CKPS0 Bit
......................................................................64
T2CKPS1 Bit
......................................................................64
T
AD
.....................................................................................85
Time-out Sequence
............................................................92
Timer0
................................................................................53
Associated Registers
.................................................55
Clock Source Edge Select (T0SE Bit)
........................17
Clock Source Select (T0CS Bit)
.................................17
External Clock
............................................................54
Interrupt
......................................................................53
Operation
...................................................................53
Overflow Enable (TMR0IE Bit)
...................................18
Overflow Flag (TMR0IF Bit)
.......................................97
Overflow Interrupt
......................................................97
Prescaler
....................................................................54
T0CKI
.........................................................................54
Timer1
................................................................................57
Associated Registers
.................................................62
Capacitor Selection
....................................................60
Counter Operation
.....................................................58
Operation
...................................................................57
Operation in Asynchronous Counter Mode
................59
Operation in Synchronized Counter Mode
.................58
Operation in Timer Mode
...........................................58
Oscillator
....................................................................60
Oscillator Layout Considerations
...............................60
Prescaler
....................................................................61
Resetting Timer1 Register Pair
..................................61
Resetting Timer1 Using a CCP
Trigger Output
....................................................60
TMR1H
.......................................................................59
TMR1L
.......................................................................59
Use as a Real-Time Clock
.........................................61
Timer2
................................................................................63
Associated Registers
.................................................64
Output
........................................................................63
Postscaler
..................................................................63
Prescaler
....................................................................63
Prescaler and Postscaler
...........................................63
Timing Diagrams
A/D Conversion
........................................................141
Brown-out Reset
......................................................132
Capture/Compare/PWM (CCP1)
..............................134
CLKO and I/O
..........................................................131
External Clock
..........................................................130
I
2
C Bus Data
............................................................138
I
2
C Bus START/STOP Bits
......................................137
I
2
C Reception (7-bit Address)
....................................78
I
2
C Transmission (7-bit Address)
...............................78
PWM Output
..............................................................68
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer
..............................132
Slow Rise Time (MCLR Tied to V
DD
Through RC Network)
........................................ 96
SPI Master Mode
....................................................... 75
SPI Master Mode (CKE = 0, SMP = 0)
.................... 135
SPI Master Mode (CKE = 1, SMP = 1)
.................... 135
SPI Slave Mode (CKE = 0)
.................................75
,
136
SPI Slave Mode (CKE = 1)
.................................75
,
136
Time-out Sequence on Power-up (MCLR Tied
to V
DD
Through Pull-up Resistor)
...................... 95
Time-out Sequence on Power-up (MCLR Tied
to V
DD
Through RC Network): Case 1
............... 95
Time-out Sequence on Power-up (MCLR Tied
to V
DD
Through RC Network): Case 2
............... 95
Timer0 and Timer1 External Clock
.......................... 133
Timer1 Incrementing Edge
........................................ 58
Wake-up from SLEEP via Interrupt
.......................... 100
Timing Parameter Symbology
......................................... 129
TMR0 Register
................................................................... 15
TMR1CS Bit
....................................................................... 57
TMR1H Register
................................................................ 13
TMR1L Register
................................................................. 13
TMR1ON Bit
...................................................................... 57
TMR2 Register
................................................................... 13
TMR2ON Bit
...................................................................... 64
TOUTPS0 Bit
..................................................................... 64
TOUTPS1 Bit
..................................................................... 64
TOUTPS2 Bit
..................................................................... 64
TOUTPS3 Bit
..................................................................... 64
TRISA Register
.............................................................14
,
39
TRISB Register
.............................................................14
,
15
V
V
DD
Pin
................................................................................ 8
V
SS
Pin
................................................................................ 8
W
Wake-up from SLEEP
...................................................89
,
99
Interrupts
..............................................................93
,
94
MCLR Reset
.............................................................. 94
WDT Reset
................................................................ 94
Wake-up Using Interrupts
.................................................. 99
Watchdog Timer (WDT)
................................................89
,
98
Associated Registers
................................................. 98
Enable (WDTEN Bit)
.................................................. 98
INTRC Oscillator
........................................................ 98
Postscaler.
See
Postscaler, WDT
Programming Considerations
.................................... 98
Time-out Period
......................................................... 98
WDT Reset, Normal Operation
.......................91
,
93
,
94
WDT Reset, SLEEP
........................................91
,
93
,
94
WCOL
................................................................................ 73
Write Collision Detect bit, WCOL
....................................... 73
WWW, On-Line Support
...................................................... 3