參數(shù)資料
型號: PIC16F819
廠商: Microchip Technology Inc.
英文描述: 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology(18/20引腳,納瓦技術(shù)增強(qiáng)FLASH微控制器)
中文描述: 18/20-Pin增強(qiáng)型閃存微控制器采用納瓦技術(shù)(18/20引腳,納瓦技術(shù)增強(qiáng)閃存微控制器)
文件頁數(shù): 30/164頁
文件大?。?/td> 3045K
代理商: PIC16F819
PIC16F818/819
DS39598C-page 28
Preliminary
2002 Microchip Technology Inc.
3.5
Reading FLASH Program Memory
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1<7>), and then set control bit RD
(EECON1<0>). Once the read control bit is set, the pro-
gram memory FLASH controller will use the second
instruction cycle to read the data. This causes the sec-
ond instruction immediately following the “
BSF
EECON1,RD
” instruction to be ignored. The data is
available in the very next cycle, in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDATH registers will hold this value until another
read, or until it is written to by the user (during a write
operation).
EXAMPLE 3-3:
FLASH PROGRAM READ
3.6
Erasing FLASH Program Memory
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the FLASH array is not
supported.
When initiating an erase sequence from the microcon-
troller itself, a block of 32 words of program memory is
erased. The Most Significant 11 bits of the
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH pro-
gram memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
For protection, the write initiate sequence for EECON2
must be used.
After the “
BSF EECON1,WR
” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two
NOP
instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not SLEEP mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
3.6.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
Load EEADRH:EEADR with address of row
being erased.
Set EEPGD bit to point to program memory; set
WREN bit to enable writes, and set FREE bit to
enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase.
2.
3.
4.
5.
6.
7.
BANKSEL EEADRH
MOVF
MOVWF
; Select Bank of EEADRH
;
; MS Byte of Program
; Address to read
;
; LS Byte of Program
; Address to read
; Select Bank of EECON1
ADDRH, W
EEADRH
MOVF
MOVWF
ADDRL, W
EEADR
BANKSEL EECON1
BSF
EECON1, EEPGD; Point to PROGRAM
; memory
EECON1, RD
; EE Read
;
; Any instructions
; here are ignored as
; program memory is
; read in second cycle
; after BSF EECON1,RD
BANKSEL EEDATA
; Select Bank of EEDATA
MOVF
EEDATA, W
; DATAL = EEDATA
MOVWF
DATAL
;
MOVF
EEDATH, W
; DATAH = EEDATH
MOVWF
DATAH
;
BSF
NOP
NOP
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PIC16F819-E/SO 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F819-E/SS 功能描述:8位微控制器 -MCU 3.5KB 256 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F819-E/SSVAO 制造商:Microchip Technology Inc 功能描述: