參數(shù)資料
型號(hào)： PIC16F628A
廠商： Microchip Technology Inc.
英文描述： 18-pin Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology(18引腳，基于FLASH的8位CMOS微控制器，使用毫微瓦特技術(shù))
中文描述： 18引腳基于閃存的8位CMOS微控制器與納瓦技術(shù)（18引腳，基于閃存的8位的CMOS微控制器，使用毫微瓦特技術(shù)）
文件頁數(shù)： 84/168頁
文件大?。?/td> 2756K
代理商： PIC16F628A
PIC16F627A/628A/648A
DS40044B-page 82
Preliminary
2004 Microchip Technology Inc.
12.3
USART Address Detect Function
12.3.1
USART 9-BIT RECEIVER WITH
ADDRESS DETECT
When the RX9 bit is set in the RCSTA register, 9 bits
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a
special provision for multi-processor communication.
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA<3>) along with the RX9 bit. The
port is now programmed such that when the last bit is
received, the contents of the receive shift register
(RSR) are transferred to the receive buffer, the ninth bit
of the RSR (RSR<8>) is transferred to RX9D, and the
receive interrupt is set if and only if RSR<8> = 1. This
feature can be used in a multi-processor system as
follows:
A master processor intends to transmit a block of data
to one of many slaves. It must first send out an address
byte that identifies the target slave. An address byte is
identified by setting the ninth bit (RSR<8>) to a ‘1’
(instead of a ‘0’ for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling
multiprocessor communication, all data bytes will be
ignored. However, if the ninth received bit is equal to a
‘1’, indicating that the received byte is an address, the
slave will be interrupted and the contents of the RSR
register will be transferred into the receive buffer. This
allows the slave to be interrupted only by addresses, so
that the slave can examine the received byte to see if it
is being addressed. The addressed slave will then clear
its ADEN bit and prepare to receive data bytes from the
master.
When ADEN is enabled (= ‘1’), all data bytes are
ignored. Following the Stop bit, the data will not be
loaded into the receive buffer, and no interrupt will
occur. If another byte is shifted into the RSR register,
the previous data byte will be lost.
The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = ‘1’). When ADEN is
disabled (= ‘0’), all data bytes are received and the 9th
bit can be used as the parity bit.
The receive block diagram is shown in Figure 12-8.
Reception
is
enabled
(RCSTA<4>).
by
setting
bit
CREN
12.3.1.1
Setting up 9-bit mode with Address
Detect
Follow these steps when setting up Asynchronous
Reception with Address Detect Enabled:
1.
TRISB<1> bit needs to be set and TRISB<2> bit
cleared in order to configure pins RB2/TX/CK
and RB1/RX/DT as the Universal Synchronous
Asynchronous Receiver Transmitter pins.
2.
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH.
3.
Enable asynchronous communication by setting
or clearing bit SYNC and setting bit SPEN.
4.
If interrupts are desired, then set enable bit
RCIE.
5.
Set bit RX9 to enable 9-bit reception.
6.
Set ADEN to enable address detect.
7.
Enable the reception by setting enable bit CREN
or SREN.
8.
Flag bit RCIF will be set when reception is
complete, and an interrupt will be generated if
enable bit RCIE was set.
9.
Read the 8-bit received data by reading the
RCREG register to determine if the device is
being addressed.
10. If any error occurred, clear the error by clearing
enable bit CREN if it was already set.
11. If the device has been addressed (RSR<8> = ‘1’
with address match enabled), clear the ADEN
and RCIF bits to allow data bytes and address
bytes to be read into the receive buffer and
interrupt the CPU.
TABLE 12-8:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
RCSTA
RCREG USART Receive data register
PIE1
EEIE
CMIE
TXSTA
CSRC
SPBRG
Legend:
x
= unknown,
-
= unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.
EEIF
SPEN
CMIF
RX9
RCIF
SREN
TXIF
CREN
—
CCP1IF TMR2IF TMR1IF
FERR
OERR
0000 -000
0000 000x
0000 0000
0000 -000
0000 000x
0000 0000
0000 -000
0000 -010
0000 0000
ADEN
RX9D
RCIE
TXEN
TXIE
SYNC
—
—
CCP1IE TMR2IE TMR1IE
0000 -000
BRGH
TRMT
TX9
TX9D
0000 -010
0000 0000
Baud Rate Generator Register
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC16F628A-E/ML 功能描述:8位微控制器 -MCU 3.5KB 224 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F628A-E/P 功能描述:8位微控制器 -MCU 3.5KB 224 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F628A-E/SO 功能描述:8位微控制器 -MCU 3.5KB 224 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F628A-E/SS 功能描述:8位微控制器 -MCU 3.5KB 224 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC16F628A-I/ML 功能描述:8位微控制器 -MCU 3.5KB 224 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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