參數(shù)資料
型號: PIC16F628A
廠商: Microchip Technology Inc.
英文描述: 18-pin Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology(18引腳,基于FLASH的8位CMOS微控制器,使用毫微瓦特技術(shù))
中文描述: 18引腳基于閃存的8位CMOS微控制器與納瓦技術(shù)(18引腳,基于閃存的8位的CMOS微控制器,使用毫微瓦特技術(shù))
文件頁數(shù): 53/168頁
文件大小: 2756K
代理商: PIC16F628A
2004 Microchip Technology Inc.
Preliminary
DS40044B-page 51
PIC16F627A/628A/648A
7.4
Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). It will
continue to run during Sleep. It is primarily intended for
a 32.768 kHz watch crystal. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 7-1:
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
7.5
Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate a “special event trigger” (CCP1M3:CCP1M0
=
1011
), this signal will Reset Timer1.
Timer1 must be configured for either timer or synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPRxH:CCPRxL
registers pair effectively becomes the period register
for Timer1.
7.6
Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other Reset except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
7.7
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 7-2:
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Freq
C1
C2
15 pF
32.768 kHz
These values are for design guidance only.
Consult AN826 (DS00826) for further information
on Crystal/Capacitor Selection.
15 pF
Note:
The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
all other
Resets
0Bh, 8Bh,
10Bh, 18Bh
0Ch
8Ch
0Eh
0Fh
10h
Legend:
INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
PIR1
PIE1
TMR1L
TMR1H
T1CON
x
= unknown,
u
= unchanged,
-
= unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.
EEIF
EEIE
CMIF
CMIE
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
T1CKPS1
T1CKPS0
T1OSCEN
RCIF
RCIE
TXIF
TXIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
0000 -000
0000 -000
0000 -000
0000 -000
xxxx xxxx
uuuu uuuu
xxxx xxxx
uuuu uuuu
T1SYNC
TMR1CS
TMR1ON
--00 0000
--uu uuuu
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