參數(shù)資料
型號: PIC16F628A
廠商: Microchip Technology Inc.
英文描述: 18-pin Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology(18引腳,基于FLASH的8位CMOS微控制器,使用毫微瓦特技術(shù))
中文描述: 18引腳基于閃存的8位CMOS微控制器與納瓦技術(shù)(18引腳,基于閃存的8位的CMOS微控制器,使用毫微瓦特技術(shù))
文件頁數(shù): 81/168頁
文件大?。?/td> 2756K
代理商: PIC16F628A
2004 Microchip Technology Inc.
Preliminary
DS40044B-page 79
PIC16F627A/628A/648A
12.2.2
USART ASYNCHRONOUS
RECEIVER
The receiver block diagram is shown in Figure 12-8.
The data is received on the RB1/RX/DT pin and drives
the data recovery block. The data recovery block is
actually a high-speed shifter operating at x16 times the
baud rate, whereas the main receive serial shifter
operates at the bit rate or at F
OSC
.
When Asynchronous mode is selected, reception is
enabled by setting bit CREN (RCSTA<4>).
The heart of the receiver is the receive (serial) shift
register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register, (i.e., it is a two deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR register. On the detection of the
Stop bit of the third byte, if the RCREG register is still
full then overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited, so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA<2>) is set if a Stop bit
is detected as clear. Bit FERR and the 9th receive bit
are buffered the same way as the receive data. Read-
ing the RCREG, will load bits RX9D and FERR with
new values, therefore it is essential for the user to read
the RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information.
FIGURE 12-8:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RB1/RX/DT
Pin Buffer
and Control
SPEN
Data
Recovery
CREN
OERR
FERR
RSR register
MSb
LSb
RX9D
RCREG register
FIFO
Interrupt
RCIF
RCIE
Data Bus
8
3 64
or
3 16
Stop
Start
(8)
7
1
0
RX9
2 2 2
RX9
ADEN
RX9
ADEN
RSR<8>
Enable
Load of
Receive
Buffer
8
8
RCREG register
RX9D
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PIC16F628A-E/SS 功能描述:8位微控制器 -MCU 3.5KB 224 RAM 16 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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