參數(shù)資料
型號: PIC14000-04
廠商: Microchip Technology Inc.
英文描述: 28-Pin Programmable Mixed Signal Controller
中文描述: 28引腳可編程混合信號控制器
文件頁數(shù): 58/152頁
文件大小: 953K
代理商: PIC14000-04
PIC14000
DS40122B-page 58
Preliminary
1996 Microchip Technology Inc.
Caution:
Reading or writing the ADTMR register
during an A/D conversion cycle can pro-
duce unpredictable results and is not
recommended.
During conversion one or both of the following events
will occur:
1.
capture event
2.
timer overflow
In a capture event, the comparator trips when the slope
voltage on the CDAC output exceeds the input voltage,
causing the comparator output to transition from high to
low. This causes a transfer of the current timer count to
the capture register and sets the ADCIF flag
(PIR1<1>).
Note:
The correct sequence for writing the
ADTMR register is HI byte followed by LO
byte. Reversing this order will prevent the
A/D timer from running.
A CPU interrupt will be generated if bit ADCIE
(PIE1<1>) is set to ‘1’ (interrupt enabled). In addition,
the Global Interrupt Enable and Peripheral Interrupt
Enables (INTCON<7,6>) must also be set. Software is
responsible for clearing the ADCIF flag prior to the next
conversion cycle. Note that this interrupt can only occur
once per conversion cycle.
In a timer overflow condition, the timer rolls over from
FFFFh to 0000h, and a capture overflow flag (OVFIF)
is asserted (PIR1<0>). The timer continues to incre-
ment following a timer overflow. A CPU interrupt can be
generated if bit OVFIE (PIE1<0>) is set (interrupt
enabled). In addition, the Global Interrupt Enable and
Peripheral Interrupt Enables (INTCON<7,6>) must also
be set. Software is responsible for clearing the OVFIF
flag prior to the next conversion cycle.
FIGURE 8-1:
A/D BLOCK DIAGRAM
(nominal)
ADOFF
WRITE_TMR
ADRST
OSC1
1
0
FOSC
(Configuration Bit)
Internal
Oscillator
ADTMRH
ADTMRL
Clock
Stop
Logic
Timer
Overflow
(OVFIF, PIR1<0>)
ADCAPH
ADCAPL
Analog
Mux
~ 1 kohm
Temp sensor
SREFLO
SREFHI
Bandgap Ref.
7
6
5
4
3
2
1
0
RA2/AN2
RA1/AN1
RA0/AN0
A/D Capture
A/D
Capture Interrupt
(ADCIF, PIR1<1>)
ADOFF
CDAC
~2.5uA~5uA~10uA~20uA
ADCON1<7:4>
~100
0.1
μ
F
ADRST (ADCON0<1>)
RA3/AN3
8
ADOFF
(SLPCON<0>)
Prog. Ref. A
RD4/AN4
RD6/AN6
9
11
12
RESERVED
13
15
AMUXOE
(ADCON0<2>)
Internal
Data
Bus
4
Note 2
Note 1:
Note 2:
All current sources are disabled if ADRST = ‘1’
Approximately 3.5 microsecond time constant
Note 1
4-Bit Current DAC
ADCON0<7:4>
RA0/AN0
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