參數(shù)資料
型號: PIC14000-04
廠商: Microchip Technology Inc.
英文描述: 28-Pin Programmable Mixed Signal Controller
中文描述: 28引腳可編程混合信號控制器
文件頁數(shù): 117/152頁
文件大小: 953K
代理商: PIC14000-04
1996 Microchip Technology Inc.
Preliminary
DS40122B-page 117
PIC14000
FIGURE 13-7: I
2
C BUS DATA TIMING
TABLE 13-8: I
2
C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
T
HIGH
Clock high time
100 kHz mode
4.0
μ
s
PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
μ
s
PIC14000 must operate at a
minimum of 10 MHz
I
2
C Module
100 kHz mode
1.5 T
CY
4.7
101
T
LOW
Clock low time
μ
s
PIC14000 must operate at a
minimum of 1.5 MHz
PIC14000 must operate at a
minimum of 10 MHz
400 kHz mode
1.3
μ
s
I
2
C Module
100 kHz mode
400 kHz mode
1.5 T
CY
20+0.1 C
b
102
T
R
SDA and SCL rise
time
1000
300
ns
ns
C
b
is specified to be from
10-400 pF
103
T
F
SDA and SCL fall
time
100 kHz mode
400 kHz mode
300
300
ns
ns
20+0.1 C
b
C
b
is specified to be from
10-400 pF
Only relevant for repeated
START condition
90
T
SU
:
STA
START condition
setup time
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
4.7
0.6
4.0
0.6
0
0
250
100
4.7
0.6
4.7
1.3
0.9
3500
μ
s
μ
s
μ
s
μ
s
ns
μ
s
ns
ns
μ
s
μ
s
ns
ns
μ
s
μ
s
91
T
HD
:
STA
START condition hold
time
After this period the first clock
pulse is generated
106
T
HD
:
DAT
Data input hold time
107
T
SU
:
DAT
Data input setup time
Note 2
92
T
SU
:
STO
STOP condition setup
time
109
T
AA
Output valid from
clock
Note 1
110
T
BUF
Bus free time
Time the bus must be free
before a new transmission
can start
C
b
Bus capacitive loading
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of STARTs or STOPs.
2: A fast-mode I
2
C-bus device can be used in a standard-mode I
2
C-bus system, but the requirement
t
SU
:DAT
250ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line T
R
max.+t
SU
:DAT=1000+250=1250 ns (according to the standard-mode I
2
C
bus specification) before the SCL line is released.
SCL
SDA
IN
SDA
OUT
90
93
100
91
101
92
102
82
92
100
99
109
99
109
81
91
96
106
97
107
103
Note: Refer to Figure 13-2 for load conditions
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