Advance Information Page 74 of 114 JUNE 2008 REVISION 1.1 13 RESET This chapter describes the p" />
參數(shù)資料
型號： PI7C8154BNAE
廠商： Pericom
文件頁數(shù)： 87/114頁
文件大小： 0K
描述： IC PCI-PCI BRIDGE ASYNC 304-PBGA
標準包裝： 27
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 304-BBGA
供應商設備封裝： 304-PBGA（31x31）
包裝： 管件
安裝類型： 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 74 of 114
JUNE 2008 REVISION 1.1
13
RESET
This chapter describes the primary interface, secondary interface, and chip reset mechanisms.
13.1
PRIMARY INTERFACE RESET
PI7C8154B has a reset input, P_RESET#. When P_RESET# is asserted, the following events
occur:
PI7C8154B immediately tri-states all primary PCI interface signals. S_AD[31:0] and
S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri-stated.
PI7C8154B performs a chip reset.
Registers that have default values are reset.
PI7C8154B samples P_REQ64# to determine whether the 64-bit extension is enabled on the
primary.
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT.
PI7C8154B is not accessible during P_RESET#. After P_RESET# is de-asserted, PI7C8154B
remains inaccessible for 16 PCI clocks before the first configuration transaction can be accepted.
13.2
SECONDARY INTERFACE RESET
The bridge is responsible for driving the secondary bus reset signals, S_RESET#. Bridge asserts
S_RESET# when any of the following conditions are met:
Signal P_RESET# is asserted. Signal S_RESET# remains asserted as long as P_RESET# is
asserted and does not de-assert until P_RESET# is de-asserted.
The secondary reset bit in the bridge control register is set. Signal S_RESET# remains asserted
until a configuration write operation clears the secondary reset bit.
The chip reset bit in the diagnostic control register is set. S_RESET# remains asserted until a
configuration write operation clears the secondary reset bit. The S_RESET# in asserting and de-
asserting edges can be asynchronous to P_CLK.
When S_RESET# is asserted, all secondary PCI interface control signals, including the secondary
grant outputs, are immediately tri-stated. Signals S_AD[31:0], S_CBE[3:0], S_PAR are driven low
for the duration of S_RESET# assertion. S_REQ64# is asserted LOW to indicate 64-bit extension
support on the secondary. All posted write and delayed transaction data buffers are reset.
Therefore, any transactions residing inside the buffers at the time of secondary reset are discarded.
When S_RESET# is asserted by means of the secondary reset bit, PI7C8154B remains accessible
during secondary interface reset and continues to respond to accesses to its configuration space
from the primary interface.
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相關代理商/技術參數(shù)
參數(shù)描述
PI7C8154BNAE-80 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154BNAI 制造商:Pericom Semiconductor Corporation 功能描述:
PI7C8154BNAIE 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8154EVB 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8154NA-33 制造商:PERICOM 功能描述:
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