- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄11720 > PI7C8154BNAE (Pericom)IC PCI-PCI BRIDGE ASYNC 304-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | PI7C8154BNAE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 37/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 304-PBGA |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 304-BBGA |
| 供應(yīng)商設(shè)備封裝： | 304-PBGA（31x31） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 29 of 112
JUNE 2008 REVISION 1.1
If extra read transactions could have side effects, for example, when accessing a FIFO, use non-
prefetchable read transactions to those locations. Accordingly, if it is important to retain the value
of the byte enable bits during the data phase, use non-prefetchable read transactions. If these
locations are mapped in memory space, use the memory read command and map the target into
non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.
2.7.3
READ PREFETCH ADDRESS BOUNDARIES
PI7C8154B imposes internal read address boundaries on read prefetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8154B stops pre-fetched data,
unless the target signals a target disconnect before the read prefetched boundary is reached. When
PI7C8154B finishes transferring this read data to the initiator, it returns a target disconnect with the
last data transfer, unless the initiator completes the transaction before all pre-fetched read data is
delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME#. Section 2.7.6 describes flow-through mode
during read operations.
Table 2-4 shows the read pre-fetch address boundaries for read transactions during non-flow-
through mode.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES
Type of Transaction
Address Space
Cache Line Size
(CLS)
Prefetch Aligned Address Boundary
Configuration Read
-
*
One DWORD (no prefetch)
I/O Read
-
*
One DWORD (no prefetch)
Memory Read
Non-Prefetchable
*
One DWORD (no prefetch)
Memory Read
Prefetchable
CLS = 0 or 16
16-DWORD aligned address boundary
Memory Read
Prefetchable
CLS = 1, 2, 4, 8
Cache line address boundary
Memory Read Line
-
CLS = 0 or 16
16-DWORD aligned address boundary
Memory Read Line
-
CLS = 1, 2, 4, 8
Cache line boundary
Memory Read Multiple
-
CLS = 0 or 16
Queue full
Memory Read Multiple
-
CLS = 1, 2, 4, 8
Second cache line boundary
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5 READ TRANSACTION PREFETCHING
Type of Transaction
Read Behavior
I/O Read
Prefetching never allowed
Configuration Read
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Memory Read
Upstream: Prefetching used or programmable
Memory Read Line
Prefetching always used
Memory Read Multiple
Prefetching always used
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
2.7.4
DELAYED READ REQUESTS
PI7C8154B treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the target is
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADM1025AARQ | IC MONITOR SYS/VOLT 5CH 16QSOP |
| ADUC832BCPZ | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 31-10 | BNC FRONT MOUNT RECEPT |
| D38999/20JD97SN | CONN RCPT 12POS WALL MNT W/SCKT |
| ADUC848BSZ62-5 | IC FLASH MCU W/16BIT ADC 52MQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154BNAE-80 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154BNAI | 制造商:Pericom Semiconductor Corporation 功能描述: |
| PI7C8154BNAIE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154EVB | 功能描述:界面開發(fā)工具 64B/66MHz 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8154NA-33 | 制造商:PERICOM 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。