Advance Information Page 19 of 112 JUNE 2008 REVISION 1.1 CONFIG66 R22 I 66MHz Configuration: T" />
參數(shù)資料
型號: PI7C8154BNAE
廠商: Pericom
文件頁數(shù): 26/114頁
文件大?。?/td> 0K
描述: IC PCI-PCI BRIDGE ASYNC 304-PBGA
標(biāo)準(zhǔn)包裝: 27
系列: *
應(yīng)用: *
接口: *
電源電壓: *
封裝/外殼: 304-BBGA
供應(yīng)商設(shè)備封裝: 304-PBGA(31x31)
包裝: 管件
安裝類型: 表面貼裝
PI7C8154B
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
Advance Information
Page 19 of 112
JUNE 2008 REVISION 1.1
CONFIG66
R22
I
66MHz Configuration: This pin indicates if the
bridge is capable of running at 66MHz operation.
Tie HIGH to set bit [21] of offset 04h of the status
register.
PMEENA#
D11
I
Power Management Enable Support: This pin
sets bits [31:27] offset DEh of the Power
Management Capabilities Register. When tied
LOW, bits [31:27] offset DEh are set to 11111 to
indicate that the secondary devices are capable of
asserting PME#. When this pin is tied HIGH, bits
[31:27] offset DEh are set to 00000 to indicate that
PI7C8154B does not support the PME# pin.
EEDATA
A22
I/O
EEPROM Data: Serial data interface to the
EEPROM
EECLK
A23
O
EEPROM Clock: Clock signal to the EEPROM
interface used during the autoload and VPD
functions
EE_EN#
AC22
I
EEPROM Enable: Set to LOW to enable
EEPROM interface
NO CONNECT
B6, AA22
-
No Connect
1.2.7
GENERAL PURPOSE I/O INTERFACE SIGNALS
Name
Pin #
Type
Description
GPIO[3:0]
K2, K3, L4, L1
TS
General Purpose I/O Data Pins: The 4 general-
purpose signals are programmable as either input-
only or bi-directional signals by writing the GPIO
output enable control register in the configuration
space.
1.2.8
JTAG BOUNDARY SCAN SIGNALS
Name
Pin #
Type
Description
TCK
N20
I
Test Clock. Used to clock state information and
data into and out of the bridge during boundary
scan.
TMS
P21
I
Test Mode Select. Used to control the state of the
Test Access Port controller.
TDO
P22
O
Test Data Output. Used as the serial output for the
test instructions and data from the test logic.
TDI
P23
I
Test Data Input. Serial input for the JTAG
instructions and test data.
TRST#
N23
I
Test Reset. Active LOW signal to reset the Test
Access Port (TAP) controller into an initialized
state.
1.2.9
POWER AND GROUND
Name
Pin #
Type
Description
VDD
A2, B1, B20, B23, D5, D6,
D10, D14, D15, D18, E22,
H4, H20, J1, J3, J21, M4,
M20, N4, R1, R23, T1, T4,
T20, W3, Y6, Y10, Y14,
Y18, Y22, AB19, AB23,
AC2, AC3, AC8, AC12,
AC16
P
Power: +3.3V Digital power.
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