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參數(shù)資料
| 型號： | PI7C8154 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 44/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8154 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 44 of 115
July 31, 2003 – Revision 1.031
To enable downstream forwarding of I/O transactions, the I/O enable bit must be set in the
command register in configuration space. All I/O transactions initiated on the primary bus
will be ignored if the I/O enable bit is not set. To enable upstream forwarding of I/O
transactions, the master enable bit must be set in the command register. If the master-
enable bit is not set, PI7C8150B ignores all I/O and memory transactions initiated on the
secondary bus.
The master-enable bit also allows upstream forwarding of memory transactions if it is set.
CAUTION
If any configuration state affecting I/O transaction forwarding is changed by a
configuration write operation on the primary bus at the same time that I/O transactions are
ongoing on the secondary bus, PI7C8150B response to the secondary bus I/O transactions
is not predictable. Configure the I/O base and limit address registers, ISA enable bit, VGA
mode bit, and VGA snoop bit before setting I/O enable and master enable bits, and change
them subsequently only when the primary and secondary PCI buses are idle.
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
PI7C8150B implements one set of I/O base and limit address registers in configuration
space that define an I/O address range per port downstream forwarding. PI7C8150B
supports 32-bit I/O addressing, which allows I/O addresses downstream of PI7C8150B to
be mapped anywhere in a 4GB I/O address space.
I/O transactions with addresses that fall inside the range defined by the I/O base and limit
registers are forwarded downstream from the primary PCI bus to the secondary PCI bus.
I/O transactions with addresses that fall outside this range are forwarded upstream from the
secondary PCI bus to the primary PCI bus.
The I/O range can be turned off by setting the I/O base address to a value greater than that
of the I/O limit address. When the I/O range is turned off, all I/O trans-actions are
forwarded upstream, and no I/O transactions are forwarded downstream. The I/O range has
a minimum granularity of 4KB and is aligned on a 4KB boundary. The maximum I/O
range is 4GB in size. The I/O base register consists of an 8-bit field at configuration
address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits
[15:12] of the I/O base address. The bottom 4 bits read only as 1h to indicate that
PI7C8150B supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed to
be 0, which naturally aligns the base address to a 4KB boundary. The 16 bits contained in
the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O
base address. All 16 bits are read/write. After primary bus reset or chip reset, the value
of the I/O base address is initialized to 0000 0000h.
The I/O limit register consists of an 8-bit field at configuration offset 1Dh and a 16-bit field
at offset 32h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O limit address.
The bottom 4 bits read only as 1h to indicate that 32-bit I/O addressing is supported. Bits
[11:0] of the limit address are assumed to be FFFh, which naturally aligns the limit address
to the top of a 4KB I/O address block. The 16 bits contained in the I/O limit upper 16 bits
register at configuration offset 32h define AD[31:16] of the I/O limit address. All 16 bits
are read/write. After primary bus reset or chip reset, the value of the I/O limit address is
reset to 0000 0FFFh.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8154-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8154-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8154ANA | 功能描述:外圍驅(qū)動器與原件 - PCI 64-Bit/66MHz 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154ANAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 64B/66MHz 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8154B | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
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