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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 22 of 115
July 31, 2003 – Revision 1.031
3
PCI BUS OPERATION
This Chapter offers information about PCI transactions, transaction forwarding across
PI7C8150B, and transaction termination. The PI7C8150B has two 128-byte FIFO’s for
buffering of upstream and downstream transactions. These hold addresses, data,
commands, and byte enables that are used for write transactions. The PI7C8150B also has
an additional four 128-byte FIFO’s that hold addresses, data, commands, and byte enables
for read transactions.
3.1
TYPES OF TRANSACTIONS
This section provides a summary of PCI transactions performed by PI7C8150B.
Table 3-1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C8150B initiates
transactions as a master, on the primary (P) and secondary (S) buses, and when PI7C8150B
responds to transactions as a target, on the primary (P) and secondary (S) buses.
Table 3-1. PCI Transactions
Types of Transactions
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
Reserved
0101
Reserved
0110
Memory Read
0111
Memory Write
1000
Reserved
1001
Reserved
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1101
Dual Address Cycle
1110
Memory Read Line
1111
Memory Write and Invalidate
Initiates as Master
Primary
N
Y
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
Responds as Target
Primary
N
N
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Secondary
N
Y
Y
Y
N
N
Y
Y
N
N
Y
Y
Y
Y
Y
Y
Secondary
N
N
Y
Y
N
N
Y
Y
N
N
N
Y (Type 1 only)
Y
Y
Y
Y
As indicated in Table 3-1, the following PCI commands are not supported by
PI7C8150B:
!
PI7C8150B never initiates a PCI transaction with a reserved command code and, as a
target, PI7C8150B ignores reserved command codes.
!
PI7C8150B does not generate interrupt acknowledge transactions. PI7C8150B
ignores interrupt acknowledge transactions as a target.
!
PI7C8150B does not respond to special cycle transactions. PI7C8150B cannot
guarantee delivery of a special cycle transaction to downstream buses because of the
broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.