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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 8 of 115
July 31, 2003 – Revision 1.031
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14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
BRIDGE BEHAVIOR.................................................................................................................. 101
15.1
BRIDGE
ACTIONS
FOR
VARIOUS
CYCLE
TYPES.............................................................. 101
15.2
ABNORMAL
TERMINATION
(INITIATED
BY
BRIDGE
MASTER)................................... 101
15.2.1
MASTER ABORT
.............................................................................................................. 101
15.2.2
PARITY AND ERROR REPORTING
.............................................................................. 101
15.2.3
REPORTING PARITY ERRORS
..................................................................................... 102
15.2.4
SECONDARY IDSEL MAPPING
.................................................................................... 102
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.............................................................. 102
16.1
BOUNDARY
SCAN
ARCHITECTURE................................................................................... 102
16.1.1
TAP PINS
.......................................................................................................................... 103
16.1.2
INSTRUCTION REGISTER
............................................................................................ 103
16.2
BOUNDARY
SCAN
INSTRUCTION
SET............................................................................... 104
16.3
TAP
TEST
DATA
REGISTERS ................................................................................................ 105
16.4
BYPASS
REGISTER................................................................................................................. 105
16.5
BOUNDARY-SCAN
REGISTER.............................................................................................. 105
16.6
TAP
CONTROLLER ................................................................................................................. 105
17
ELECTRICAL AND TIMING SPECIFICATIONS................................................................. 109
17.1
MAXIMUM
RATINGS ............................................................................................................. 109
17.2
DC
SPECIFICATIONS.............................................................................................................. 109
17.3
AC
SPECIFICATIONS.............................................................................................................. 110
17.4
66MHZ
TIMING........................................................................................................................ 111
17.5
33MHZ
TIMING........................................................................................................................ 111
17.6
POWER
CONSUMPTION......................................................................................................... 111
18
PACKAGE INFORMATION...................................................................................................... 112
18.1
208-PIN
FQFP
PACKAGE
DIAGRAM..................................................................................... 112
18.2
256-BALL
PBGA
PACKAGE
DIAGRAM................................................................................ 113
18.3
PART
NUMBER
ORDERING
INFORMATION...................................................................... 113
RETRY COUNTER REGISTER – OFFSET 78h
.......................................................... 98
PRIMARY MASTER TIMEOUT COUNTER – OFFSET 80h
..................................... 98
SECONDARY MASTER TIMEOUT COUNTER – OFFSET 80h
............................... 98
CAPABILITY ID REGISTER – OFFSET B0h
............................................................. 98
NEXT POINTER REGISTER – OFFSET B0h
............................................................. 98
SLOT NUMBER REGISTER – OFFSET B0h
.............................................................. 99
CHASSIS NUMBER REGISTER – OFFSET B0h
....................................................... 99
CAPABILITY ID REGISTER – OFFSET DCh
............................................................. 99
NEXT ITEM POINTER REGISTER – OFFSET DCh
................................................. 99
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh
................. 99
POWER MANAGEMENT DATA REGISTER – OFFSET E0h
................................. 100
CAPABILITY ID REGISTER – OFFSET E4h
........................................................... 100
NEXT POINTER REGISTER – OFFSET E4h
........................................................... 100
15