參數(shù)資料
型號(hào)： PI7C8150B-33
英文描述： PCI Bridge | Asynchronous 2-Port PCI Bridge
中文描述： PCI橋|異步2端口PCI橋
文件頁(yè)數(shù)： 5/115頁(yè)
文件大?。?/td> 879K
代理商： PI7C8150B-33
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 5 of 115
July 31, 2003 – Revision 1.031
TABLE OF CONTENTS
1
INTRODUCTION.............................................................................................................................. 11
2
SIGNAL DEFINITIONS ................................................................................................................... 12
2.1
S
IGNAL
T
YPES
............................................................................................................................... 12
2.2
S
IGNALS
........................................................................................................................................ 12
2.2.1
PRIMARY BUS INTERFACE SIGNALS
.......................................................................... 12
2.2.3
CLOCK SIGNALS
............................................................................................................... 15
2.2.4
MISCELLANEOUS SIGNALS
........................................................................................... 16
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
........................................................ 17
2.2.6
JTAG BOUNDARY SCAN SIGNALS
................................................................................ 17
2.2.7
POWER AND GROUND
..................................................................................................... 18
2.3
PIN
LIST
–
208-PIN
FQFP........................................................................................................... 18
2.4
PIN
LIST
–
256-BALL
PBGA...................................................................................................... 20
PCI BUS OPERATION..................................................................................................................... 22
3.1
TYPES
OF
TRANSACTIONS..................................................................................................... 22
3.2
SINGLE
ADDRESS
PHASE........................................................................................................ 23
3.3
DEVICE
SELECT
(DEVSEL_L)
GENERATION....................................................................... 23
3.4
DATA
PHASE.............................................................................................................................. 23
3.5
WRITE
TRANSACTIONS .......................................................................................................... 23
3.5.1
MEMORY WRITE TRANSACTIONS
................................................................................ 24
3.5.2
MEMORY WRITE AND INVALIDATE
............................................................................ 25
3.5.3
DELAYED WRITE TRANSACTIONS
............................................................................... 25
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES
....................................................... 26
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS
..................................................... 26
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
....................................................................... 27
3.6
READ
TRANSACTIONS............................................................................................................ 27
3.6.1
PREFETCHABLE READ TRANSACTIONS
.................................................................... 27
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS
.......................................................... 27
3.6.3
READ PREFETCH ADDRESS BOUNDARIES
............................................................... 28
3.6.4
DELAYED READ REQUESTS
.......................................................................................... 29
3.6.5
DELAYED READ COMPLETION WITH TARGET
........................................................ 29
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS
................................................ 29
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
............................................................. 30
3.7
CONFIGURATION
TRANSACTIONS...................................................................................... 30
3.7.1
TYPE 0 ACCESS TO PI7C8150B
....................................................................................... 31
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
.................................................................................. 31
3.7.3
TYPE 1 TO TYPE 1 FORWARDING
................................................................................. 33
3.7.4
SPECIAL CYCLES
............................................................................................................. 34
3.8
TRANSACTION
TERMINATION.............................................................................................. 34
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150B
................................................. 35
3.8.2
MASTER ABORT RECEIVED BY PI7C8150B
................................................................ 36
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150B
.................................................. 36
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150B
.................................................. 41
ADDRESS DECODING..................................................................................................................... 43
4.1
ADDRESS
RANGES................................................................................................................... 43
4.2
I/O
ADDRESS
DECODING........................................................................................................ 43
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER
................................................................ 44
4.2.2
ISA MODE
........................................................................................................................... 45
3
4
相關(guān)PDF資料
PDF描述
PI7C8152B PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8154 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8154-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150BEVB 功能描述:界面開(kāi)發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8150BMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMA-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BMAI 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*