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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 6 of 115
July 31, 2003 – Revision 1.031
4.3
MEMORY
ADDRESS
DECODING............................................................................................ 45
4.3.1
MEMORY-MAPPED I/O BASE AND LIMIT ADDRESS REGISTERS
......................... 46
4.3.2
PREFETCHABLE MEMORY BASE AND LIMIT ADDRESS REGISTERS
................. 47
4.4
VGA
SUPPORT........................................................................................................................... 48
4.4.1
VGA MODE
......................................................................................................................... 48
4.4.2
VGA SNOOP MODE
........................................................................................................... 48
TRANSACTION ORDERING.......................................................................................................... 49
5.1
TRANSACTIONS
GOVERNED
BY
ORDERING
RULES........................................................ 49
5.2
GENERAL
ORDERING
GUIDELINES...................................................................................... 50
5.3
ORDERING
RULES.................................................................................................................... 50
5.4
DATA
SYNCHRONIZATION.................................................................................................... 53
ERROR HANDLING......................................................................................................................... 54
6.1
ADDRESS
PARITY
ERRORS .................................................................................................... 54
6.2
DATA
PARITY
ERRORS............................................................................................................ 55
6.2.1
CONFIGURATION WRITE TRANSACTIONS TO CONFIGURATION SPACE
.......... 55
6.2.2
READ TRANSACTIONS
.................................................................................................... 55
6.2.3
DELAYED WRITE TRANSACTIONS
............................................................................... 56
6.2.4
POSTED WRITE TRANSACTIONS
.................................................................................. 59
6.3
DATA
PARITY
ERROR
REPORTING
SUMMARY ................................................................. 60
6.4
SYSTEM
ERROR
(SERR_L)
REPORTING ............................................................................... 65
EXCLUSIVE ACCESS...................................................................................................................... 66
7.1
CONCURRENT
LOCKS............................................................................................................. 66
7.2
ACQUIRING
EXCLUSIVE
ACCESS
ACROSS
PI7C8150B..................................................... 66
7.2.1
LOCKED TRANSACTIONS IN DOWNSTREAM DIRECTION
..................................... 67
7.2.2
LOCKED TRANSACTION IN UPSTREAM DIRECTION
.............................................. 68
7.3
ENDING
EXCLUSIVE
ACCESS................................................................................................ 68
PCI BUS ARBITRATION................................................................................................................. 69
8.1
PRIMARY
PCI
BUS
ARBITRATION......................................................................................... 69
8.2
SECONDARY
PCI
BUS
ARBITRATION .................................................................................. 69
8.2.1
SECONDARY BUS ARBITRATION USING THE INTERNAL ARBITER
.................... 70
8.2.2
PREEMPTION
.................................................................................................................... 71
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL ARBITER
...................... 71
8.2.4
BUS PARKING
.................................................................................................................... 71
CLOCKS............................................................................................................................................. 72
9.1
PRIMARY
CLOCK
INPUTS....................................................................................................... 72
9.2
SECONDARY
CLOCK
OUTPUTS............................................................................................. 72
9.3
ASYNCHRONOUS
MODE......................................................................................................... 72
10
GENERAL PURPOSE I/O INTERFACE.................................................................................... 73
10.1
GPIO
CONTROL
REGISTERS................................................................................................... 73
10.2
SECONDARY
CLOCK
CONTROL............................................................................................ 74
10.3
LIVE
INSERTION....................................................................................................................... 76
11
PCI POWER MANAGEMENT.................................................................................................... 76
5
6
7
8
9
12
RESET............................................................................................................................................. 77
12.1
PRIMARY
INTERFACE
RESET................................................................................................ 77
12.2
SECONDARY
INTERFACE
RESET.......................................................................................... 77
12.3
CHIP
RESET................................................................................................................................ 78