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參數(shù)資料
| 型號： | PI7C8150A |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 58/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150A |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 58 of 115
July 31, 2003 – Revision 1.031
!
PI7C8150B first asserts P_TRDY_L and then asserts P_PERR_L two cycles later, if
the primary interface parity-error-response bit is set in the command register.
!
!
PI7C8150B sets the primary interface parity-error-detected bit in the status register.
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
Similarly, for upstream delayed write transactions, when the parity error is detected on the
initiator bus and PI7C8150B has write status to return, the following events occur:
!
PI7C8150B first asserts S_TRDY_L and then asserts S_PERR_L two cycles later, if
the secondary interface parity-error-response bit is set in the bridge control register
(offset 3Ch).
!
PI7C8150B sets the secondary interface parity-error-detected bit in the secondary
status register.
!
Because there was not an exact data and parity match, the write status is not returned
and the transaction remains in the queue.
For downstream transactions, where the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
!
PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the following are
both true:
!
The parity-error-response bit is set in the command register of the primary
interface.
!
The parity-error-response bit is set in the bridge control register of the
secondary interface.
!
PI7C8150B completes the transaction normally.
For upstream transactions, when the parity error is being passed back from the target bus
and the parity error condition was not originally detected on the initiator bus, the following
events occur:
!
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the following are
both true:
!
The parity error response bit is set in the command register of the primary
interface.
!
The parity error response bit is set in the bridge control register of the
secondary interface.
!
PI7C8150B completes the transaction normally.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
| PI7C8150AMAE | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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