參數資料
型號： PI7C8150A
英文描述： PCI Bridge | 2-Port PCI-to-PCI Bridge
中文描述： PCI橋| 2端口PCI至PCI橋
文件頁數： 56/115頁
文件大小： 879K
代理商： PI7C8150A
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 56 of 115
July 31, 2003 – Revision 1.031
!
PI7C8150B sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
!
PI7C8150B forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
primary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
!
For upstream transactions, when PI7C8150B detects a read data parity error on the primary
bus, the following events occur:
!
PI7C8150B asserts P_PERR_L two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
!
PI7C8150B sets the detected parity error bit in the primary status register.
!
PI7C8150B sets the data parity detected bit in the primary status register, if the
primary interface parity-error-response bit is set in the command register.
!
PI7C8150B forwards the bad parity with the data back to the initiator on the secondary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the
secondary bus, the data is discarded and the data with bad parity is not returned to the
initiator.
!
PI7C8150B completes the transaction normally.
PI7C8150B returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR_L two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C8150B detects PERR_L asserted while returning read data to the initiator, PI7C8150B
does not take any further action and completes the transaction normally.
PI7C8150B completes the transaction normally.
6.2.3
DELAYED WRITE TRANSACTIONS
When PI7C8150B detects a data parity error during a delayed write transaction, the
initiator drives data and data parity, and the target checks parity and conditionally asserts
PERR_L.
For delayed write transactions, a parity error can occur at the following times:
!
During the original delayed write request transaction
!
When the initiator repeats the delayed write request transaction
!
When PI7C8150B completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is returned to
相關PDF資料
PDF描述
PI7C8150A-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150B PCI Bridge | Asynchronous 2-Port PCI Bridge
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PI7C81552 ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C81552A ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
相關代理商/技術參數
參數描述
PI7C8150A-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150AMA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP
PI7C8150AMA-33 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP
PI7C8150AMAE 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150AMAE-33 功能描述:外圍驅動器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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