參數(shù)資料
型號(hào)： PI7C7100BNA
英文描述： PCI Bus Interface/Controller
中文描述： PCI總線接口/控制器
文件頁數(shù)： 51/118頁
文件大小： 2962K
代理商： PI7C7100BNA
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05/08/00
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8. Exclusive Access
PI7C7100
ADVANCE INFORMATION
This chapter describes the use of the LOCK# signal to implement exclusive access to a target for transactions that cross
PI7C7100.
8.1 Concurrent Locks
The primary and secondary bus lock mechanisms operate concurrently except when a locked transaction crosses
PI7C7100. A primary master can lock a primary target without affecting the status of the lock on the secondary bus, and
vice versa. This means that a primary master can lock a primary target at the same time that a secondary master locks
a secondary target.
8.2 Acquiring Exclusive Access across PI7C7100
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked transactions, the initiator
must first check that both of the following conditions are met:
The PCI bus must be idle.
The LOCK# signal must be de-asserted.
The initiator leaves the LOCK# signal de-asserted during the address phase and asserts LOCK# one clock cycle later.
Once a data transfer is completed from the target, the target lock has been achieved.
Locked transactions can cross PI7C7100 in the downstream and upstream directions, from the primary bus to the
secondary bus and vice versa.
When the target resides on another PCI bus, the master must acquire not only the lock on its own PCI bus but also the
lock on every bus between its bus and the targets bus. When PI7C7100 detects on the primary bus, an initial locked
transaction intended for a target on the secondary bus, PI7C7100 samples the address, transaction type, byte enable bits,
and parity, as described in Section 4.6.4. It also samples the lock signal. If there is a lock established between 2 ports
or the target bus is already locked by another master, then the current lock cycle is re3ed without forward. Because a
target retry is signaled to the initiator, the initiator must relinquish the lock on the primary bus, and therefore the lock is
not yet established.
The first locked transaction must be a read transaction. Subsequent locked transactions can be read or write transactions.
Posted memory write transactions that are a part of the locked transaction sequence are still posted. Memory read
transactions that are a part of the locked transaction sequence are not pre-fetched.
When the locked delayed read request is queued, PI7C7100 does not queue any more transactions until the locked
sequence is finished. PI7C7100 signals a target retry to all transactions initiated subsequent to the locked read transaction
that are intended for targets on the other side of PI7C7100. PI7C7100 allows any transactions queued before the locked
transaction to complete before initiating the locked transaction.
When the locked delayed read request transaction moves to the head of the delayed transaction queue, PI7C7100 initiates
the transaction as a locked read transaction by de-asserting LOCK# on the target bus during the first address phase, and
by asserting LOCK# one cycle later. If LOCK# is already asserted (used by another initiator), PI7C7100 waits to request
access to the secondary bus until LOCK# is de-asserted when the target bus is idle. Note that the existing lock on the
target bus could not have crossed PI7C7100. Otherwise, the pending queued locked transaction would not have been
queued. When PI7C7100 is able to complete a data transfer with the locked read transaction, the lock is established on
the secondary bus.
When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and
byte enable bits, PI7C7100 transfers the read data back to the initiator, and the lock is then also established on the primary
bus.
For PI7C7100 to recognize and respond to the initiator, the initiators subsequent attempts of the read transaction must
use the locked transaction sequence (de-assert LOCK# during address phase, and assert LOCK# one cycle later). If the
LOCK# sequence is not used in subsequent attempts, a master timeout condition may result. When a master timeout
condition occurs, SERR# is conditionally asserted (see Section 7.4), the read data and queued read transaction are
discarded, and the LOCK# signal is de-asserted on the target bus.
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