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參數(shù)資料
| 型號： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 4/118頁 |
| 文件大小： | 2962K |
| 代理商： | PI7C7100BNA |
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iv
05/08/00
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PI7C7100
ADVANCE INFORMATION
5.
5.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
6.
6.1
6.2
6.3
6.4
7.
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.4
8.
8.1
8.2
8.3
9.
9.1
9.2
9.2.1
9.2.2
9.2.3
10.
10.1
10.2
11.
11.1
11.2
11.3
12.
12.1
12.2
13.
13.1
13.2
Address Decoding
..................................................................................................................................................25
Address Ranges..................................................................................................................................................... 25
I/O Address Decoding ...........................................................................................................................................25
I/O Base and Limit Address Registers ...................................................................................................................25
ISA Mode............................................................................................................................................................... 26
Memory Address Decoding................................................................................................................................... 26
Memory-Mapped I/O Base and Limit Address Registers......................................................................................26
Prefetchable Memory Base and Limit Address Registers......................................................................................27
VGA Support.......................................................................................................................................................... 28
VGA Mode .............................................................................................................................................................28
VGA Snoop Mode..................................................................................................................................................28
Transaction Ordering
...........................................................................................................................................29
Transactions Governed by Ordering Rules ........................................................................................................... 29
General Ordering Guidelines .................................................................................................................................. 29
Ordering Rules .......................................................................................................................................................30
Data Synchronization............................................................................................................................................. 31
Error Handling
...................................................................................................................................................... 32
Address Parity Errors............................................................................................................................................. 32
Data Parity Errors ................................................................................................................................................... 32
Configuration Write Transactions to Configuration Space................................................................................... 32
Read Transactions .................................................................................................................................................33
Delayed Write Transactions .................................................................................................................................. 33
Posted Write Transactions .................................................................................................................................... 35
Data Parity Error Reporting Summary ....................................................................................................................36
System Error (SERR#) Reporting ........................................................................................................................... 42
Exclusive Access
................................................................................................................................................... 43
Concurrent Locks................................................................................................................................................... 43
Acquiring Exclusive Access across PI7C7100.......................................................................................................43
Ending Exclusive Access ....................................................................................................................................... 44
PCI Bus Arbitration
.............................................................................................................................................. 45
Primary PCI Bus Arbitration................................................................................................................................... 45
Secondary PCI Bus Arbitration ............................................................................................................................. 45
Secondary Bus Arbitration Using the Internal Arbiter.......................................................................................... 45
Secondary Bus Arbitration Using an External Arbiter...........................................................................................46
Bus Parking ............................................................................................................................................................ 46
Clocks
....................................................................................................................................................................47
Primary Clock Inputs .............................................................................................................................................. 47
Secondary Clock Outputs ......................................................................................................................................47
Reset
...................................................................................................................................................................... 48
Primary Interface Reset .......................................................................................................................................... 48
Secondary Interface Reset .....................................................................................................................................48
Chip Reset ..............................................................................................................................................................48
Supported Commands
............................................................................................................................................49
Primary Interface .................................................................................................................................................... 49
Secondary Interface ............................................................................................................................................... 51
Configuration Registers
....................................................................................................................................... 52
Config Register 1.................................................................................................................................................... 52
Config Register 2.................................................................................................................................................... 53
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
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