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參數(shù)資料
| 型號(hào)： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁(yè)數(shù)： | 27/118頁(yè) |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
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PI7C7100
ADVANCE INFORMATION
PI7C7100 also supports Type 1 to Type 1 forwarding of configuration write transactions upstream to support upstream
special cycle generation. A Type 1 configuration command is forwarded upstream when the following conditions are met:
The lowest two address bits are equal to 01b.
The bus number falls outside the range defined by the lower limit (inclusive) in the secondary bus number register and
the upper limit (inclusive) in the subordinate bus number register.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The bus command is a configuration write transaction.
The PI7C7100 forwards Type 1 to Type 1 configuration write transactions as delayed transactions. Type 1 to Type 1
configuration write transactions are limited to a single data transfer.
4.7.4 Special Cycles
The Type 1 configuration mechanism is used to generate special cycle transactions in hierarchical PCI systems. Special
cycle transactions are ignored by acting as a target and are not forwarded across the bridge. Special cycle transactions
can be generated from Type 1 configuration write transactions in either the upstream or the downstream direction.
PI7C7100 initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on
the initiating bus and the following conditions are met during the address phase:
The lowest two address bits on AD[1:0] are equal to 01b.
The device number in address bits AD[15:11] is equal to 11111b.
The function number in address bits AD[10:8] is equal to 111b.
The register number in address bits AD[7:2] is equal to 000000b.
The bus number is equal to the value in the secondary bus number register in configuration space for downstream
forwarding or equal to the value in the primary bus number register in configuration space for upstream forwarding.
The bus command on CBE# is a configuration write command.
When PI7C7100 initiates the transaction on the target interface, the bus command is changed from configuration write
to special cycle. The address and data are forwarded unchanged. Devices that use special cycles ignore the address and
decode only the bus command. The data phase contains the special cycle message. The transaction is forwarded as a
delayed transaction, but in this case the target response is not forwarded back (because special cycles result in a master
abort). Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C7100
responds with TRDY# to the next attempt of the configuration transaction from the initiator. If more than one data transfer
is requested, PI7C7100 responds with a target disconnect operation during the first data phase.
4.8 Transaction Termination
This section describes how PI7C7100 returns transaction termination conditions back to the initiator.
The initiator can terminate transactions with one of the following types of termination:
Normal termination
Normal termination occurs when the initiator de-asserts FRAME# at the beginning of the last data phase, and de-
asserts IRDY# at the end of the last data phase in conjunction with either TRDY# or STOP# assertion from the
target.
Master abort
A master abort occurs when no target response is detected. When the initiator does not detect a DEVSEL# from
the target within five clock cycles after asserting FRAME#, the initiator terminates the transaction with a master
abort. If FRAME# is still asserted, the initiator de-asserts FRAME# on the next cycle, and then de-asserts IRDY#
on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is
already de-asserted, IRDY# can be de-asserted on the next clock cycle following detection of the master abort
condition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開(kāi)發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
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