- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C7100BNA PCI Bus Interface/Controller PDF資料下載
參數(shù)資料
| 型號： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 109/118頁 |
| 文件大?。?/td> | 2962K |
| 代理商： | PI7C7100BNA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁當前第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567
Appendix B
PI7C7100
3-Port PCI Bridge
B-5
04/18/00
ADVANCE INFORMATION
Frequently Asked Questions
1.
What is the function of SCAN_EN
SCAN_EN is for a full scan test or S_CLKIN select. During SCAN mode, SCAN_EN will be driven to logic 0
or logic 1 depending on functionality. During normal mode, if SCAN_EN is connected to logic 0 (JP7 in
the 1-2 position), S_CLKIN will be used for PLL test only when PL_TM is active. If SCAN_EN is connected to
logic 1 (JP7 in the 2-3 position), S_CLKIN will be the clock input for the secondary buses. All secondary
clock outputs, S_CLKOUT [15:0], are still derived from P_CLK with 0-10ns delay. The S_CLKOUT [15:0]
should be disabled by programming the bits [15:0] in both configuration registers 1 and 2 at offset 68h.
What is the function of SCAN_TM#
SCAN_TM# is for full scan test and power on reset for the PLL. SCAN_TM# should be connected to logic 1 or
to an RC path (R1 and C13) during normal operation.
How do you use the external arbiter
a)
Disable the on chip arbiter by connecting S_CFN to logic 1 (JP4 in the 2-3 position).
b)
Use S1_REQ0# as GRANT and S1_GNT0# as REQUEST on the S1 bus.
c)
Use S2_REQ0# as GRANT and S2_GNT0# as REQUEST on the S2 bus.
What is the purpose of having JP1, JP2, and JP3
JP1, JP2, and JP3 are designed for easy access to the primary bus signals. You may connect any of these pins
to an oscilloscope or a logic analyzer for observation. No connection is required for normal operation. The
following table indicates which bus signals correspond to which pins.
2.
3.
4.
5.
What is the purpose for having U17, U19, and U20
U17, U19, and U20 are designed for easy access to the digital ground planes for observation.
How is the evaluation board constructed
6.
The evaluation board is a six-layer PCB. The top and bottom layers (1 and 6) are for signals, power, and ground
routing. Layer 2 and layer 5 are ground planes. Layer 3 is a digital 3.3V power plane. Layer 4 is a digital 5V
power plane with an island of analog 3.3V power.
What is the function of S_CLKIN
7.
The S_CLKIN pin is a test pin for the on chip PLL when PLL_TM is set to logic 1. During normal operation, if
PLL_TM is set to logic 0, SCAN_TM# is set to logic 1, and SCAN_EN is set to logic 1, then S_CLKIN will
be the clock input for both the secondary buses. However, the S_CLKOUT [15:0] are still derived by program-
ming bits [15:0] in both configuration registers 1 and 2 at offset 68h.
What clock frequency combinations does the PI7C7100 support
8.
Primary Bus
Secondary (1 and 2) Buses
33MHz
How are the JTAG signals being connected
33MHz
9.
The JTAG signals consist of TRST#, TCK, TMS, TDI, and TDO. All the mentioned signals have weak internal
pull-up connections. Therefore, no connection is needed if you want the JTAG circuit to be disabled. If you want
to activate the JTAG circuit, you need to connect all five signals according to the JTAG specification (IEEE
1149).
1
2
3
4
5
6
7
8
9
0
1
1
1
2
1
3
1
4
1
5
1
6
1
2
P
J
Q
E
R
9
2
D
A
6
2
D
A
3
E
B
C
1
2
D
A
8
1
D
A
2
E
B
C
Y
D
R
I
K
C
O
L
R
A
P
4
1
D
A
1
1
D
A
0
E
B
C
6
D
A
5
D
A
0
D
A
3
P
J
1
3
D
A
8
2
D
A
5
2
D
A
3
2
D
A
0
2
D
A
7
1
D
A
E
M
A
R
F
L
E
S
V
D
R
R
E
P
1
E
B
C
3
1
D
A
0
1
D
A
8
D
A
4
D
A
2
D
A
D
N
G
1
P
J
T
N
G
0
3
D
A
7
2
D
A
4
2
D
A
2
2
D
A
9
1
D
A
6
1
D
A
Y
D
R
I
P
O
T
S
R
R
E
S
5
1
D
A
2
1
D
A
9
D
A
7
D
A
3
D
A
1
D
A
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。