參數(shù)資料
型號(hào): PHT8N06
廠商: NXP Semiconductors N.V.
英文描述: TrenchMOS transistor Standard level FET
中文描述: TrenchMOS晶體管標(biāo)準(zhǔn)電平場(chǎng)效應(yīng)管
文件頁(yè)數(shù): 1/10頁(yè)
文件大?。?/td> 72K
代理商: PHT8N06
Philips Semiconductors
Product specification
TrenchMOS
transistor
Standard level FET
PHT8N06T
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel enhancement mode logic
level field-effect power transistor in a
plastic envelope suitable for surface
mounting. Using
’trench’
technolgy
thedevice features very low on-state
resistance and has integral zener
diodes giving ESD protection. It is
intended
for
use
converters and
switching applications.
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current
Total power dissipation
Junction temperature
Drain-source on-state
resistance
55
7.5
1.8
150
80
V
A
W
C
m
in
DC-DC
V
GS
= 10 V
general purpose
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
CONDITIONS
-
R
GS
= 20 k
-
T
= 25 C
On PCB in Fig.2
T
= 25 C
On PCB in Fig.2
T
amb
= 100 C
T
sp
= 25 C
T
= 25 C
On PCB in Fig.2
T
amb
= 25 C
-
MIN.
-
-
-
-
-
MAX.
55
55
20
7.5
3.5
UNIT
V
V
V
A
A
I
D
Drain current (DC)
-
2.2
A
I
DM
P
tot
P
tot
Drain current (pulse peak value)
Total power dissipation
Total power dissipation
-
-
-
40
8.3
1.8
A
W
W
T
stg
, T
j
Storage & operating temperature
- 55
150
C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage
CONDITIONS
Human body model
(100 pF, 1.5 k
)
MIN.
-
MAX.
2
UNIT
kV
d
g
s
4
1
2
3
December 1997
1
Rev 1.100
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