參數(shù)資料
型號: PHD36N03LT
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: N-channel TrenchMOS logic level FET
中文描述: 43.4 A, 30 V, 0.017 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-252
封裝: PLASTIC, SC-63, DPAK-3
文件頁數(shù): 5/13頁
文件大?。?/td> 89K
代理商: PHD36N03LT
PHD_PHP36N03LT_2
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 02 — 8 June 2006
5 of 13
Philips Semiconductors
PHD/PHP36N03LT
N-channel TrenchMOS logic level FET
6.
Characteristics
Table 5.
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown
voltage
Characteristics
Conditions
Min
Typ
Max
Unit
I
D
= 250
μ
A; V
GS
= 0 V
T
j
= 25
°
C
T
j
=
55
°
C
I
D
= 250
μ
A; V
DS
= V
GS
; see
Figure 9
and
10
T
j
= 25
°
C
T
j
= 175
°
C
T
j
=
55
°
C
V
DS
= 24 V; V
GS
= 0 V
T
j
= 25
°
C
T
j
= 175
°
C
V
GS
=
±
20 V; V
DS
= 0 V
V
GS
= 4.5 V; I
D
= 12 A; see
Figure 6
and
8
T
j
= 25
°
C
T
j
= 175
°
C
V
GS
= 10 V; I
D
= 25 A; see
Figure 6
and
8
V
GS
= 3.5 V; I
D
= 5.2 A; see
Figure 6
and
8
30
27
-
-
-
-
V
V
V
GS(th)
gate-source threshold voltage
1
0.5
-
1.5
-
-
2
-
2.2
V
V
V
I
DSS
drain leakage current
-
-
-
0.05
-
10
1
500
100
μ
A
μ
A
nA
I
GSS
R
DSon
gate leakage current
drain-source on-state
resistance
-
-
-
-
18
32.4
14
22
22
39.6
17
40
m
m
m
m
Dynamic characteristics
Q
G(tot)
total gate charge
Q
GS
gate-source charge
Q
GD
gate-drain charge
C
iss
input capacitance
C
oss
output capacitance
C
rss
reverse transfer capacitance
t
d(on)
turn-on delay time
t
r
rise time
t
d(off)
turn-off delay time
t
f
fall time
Source-drain diode
V
SD
source-drain voltage
I
D
= 36 A; V
DS
= 15 V; V
GS
= 10 V;
see
Figure 11
and
12
-
-
-
-
-
-
-
-
-
-
18.5
4.2
2.9
690
160
110
6
10
33
19
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
see
Figure 14
V
DS
= 15 V; R
L
= 0.6
; V
GS
= 10 V;
R
G
= 10
I
S
= 25 A; V
GS
= 0 V; see
Figure 13
-
0.97
1.2
V
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