參數(shù)資料
型號: PH28F128W18BD60A
廠商: INTEL CORP
元件分類: PROM
英文描述: 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56
封裝: 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56
文件頁數(shù): 91/106頁
文件大小: 1496K
代理商: PH28F128W18BD60A
Intel
Wireless Flash Memory (W18)
Datasheet
Intel Wireless Flash Memory (W18)
07-Dec-2005
Order Number: 290701, Revision: 015
85
5
R
Reserved
5
4
R
Reserved
5
3
BW
Burst Wrap
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by
CR[2:0].(Default)
2-0
BL[2:0]
Burst Length
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16-Word Burst
111 = Continuous Burst (Default)
4
Notes:
1.
Undocumented combinations of bits are reserved by Intel for future implementations.
2.
Synchronous and page read mode configurations affect reads from main blocks and parameter
blocks. Status Register and configuration reads support single read cycles. RCR[15]=1 disables
configuration set by RCR[14:0].
3.
Data is not ready when WAIT is asserted.
4.
Set the synchronous burst length. In asynchronous page mode, the page size equals four words.
5.
Set all reserved Read Configuration Register bits to zero.
6.
Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2
(RCR[13:11] = 010), data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before
delay (RCR[8] =1) is not supported.
Table 28.
Read Configuration Register Descriptions (Sheet 2 of 2)
Bit
Name
Description1
Notes
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