參數資料
型號: PH28F128W18BD60A
廠商: INTEL CORP
元件分類: PROM
英文描述: 8M X 16 FLASH 1.8V PROM, 60 ns, PBGA56
封裝: 9 X 11 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-56
文件頁數: 37/106頁
文件大?。?/td> 1496K
代理商: PH28F128W18BD60A
Intel
Wireless Flash Memory (W18)
07-Dec-2005
Intel Wireless Flash Memory (W18)
Datasheet
36
Order Number: 290701, Revision: 015
Notes:
1.
Section 14.2, “First Access Latency Count (RCR[13:11])” on page 86 describes how to insert clock cycles during the initial
access.
2.
WAIT (shown asserted; RCR[10]=0) can be configured to assert either during, or one data cycle before, valid data.
3.
This waveform illustrates the case in which an x-word burst is initiated to the main array and it is terminated by a CE# de-
assertion after the first word in the burst. If this access had been done to Status, ID, or Query reads, the asserted (low)
WAIT signal would have remained asserted (low) as long as CE# is asserted (low).
Figure 9.
Single Synchronous Read-Array Operation Waveform
R12
R13
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