參數(shù)資料
型號： PF48F4400P0VBQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝： 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù)： 53/102頁
文件大?。?/td> 1609K
代理商： PF48F4400P0VBQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
53
10.0
Read Operations
The device supports two read modes: asynchronous page mode and synchronous burst mode.
Asynchronous page mode is the default read mode after device power-up or a reset. The Read
Configuration Register must be configured to enable synchronous burst reads of the flash memory
array (see
Section 10.3, “Read Configuration Register” on page 54
).
The device can be in any of four read states: Read Array, Read Identifier, Read Status or Read
Query. Upon power-up, or after a reset, the device defaults to Read Array. To change the read state,
the appropriate read command must be written to the device (see
Section 9.2, “Device Commands”
on page 50
). See
Section 14.0, “Special Read States” on page 75
for details regarding Read Status,
Read ID, and CFI Query modes.
The following sections describe read-mode operations in detail.
10.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read mode and the
device is set to Read Array. However, to perform array reads after any other device operation (e.g.
write operation), the Read Array command must be issued in order to read from the flash memory
array.
Note:
Asynchronous page-mode reads can only be performed when Read Configuration Register bit
RCR[15] is set (see
Section 10.3, “Read Configuration Register” on page 54
).
To perform an asynchronous page-mode read, an address is driven onto the Address bus, and CE#
and ADV# are asserted. WE# and RST# must already have been deasserted. WAIT is deasserted
during asynchronous page mode. ADV# can be driven high to latch the address, or it must be held
low throughout the read cycle. CLK is not used for asynchronous page-mode reads, and is ignored.
If only asynchronous reads are to be performed, CLK should be tied to a valid V
IH
level, WAIT
signal can be floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after
an initial access time t
AVQV
delay. (see
Section 7.0, “AC Characteristics” on page 33
).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash memory
array and loaded into an internal page buffer. The buffer word corresponding to the initial address
on the Address bus is driven onto DQ[15:0] after the initial access delay. The lowest two address
bits determine which word of the 4-word page is output from the data buffer at any given time.
10.2
Synchronous Burst-Mode Read
To perform a synchronous burst- read, an initial address is driven onto the Address bus, and CE#
and ADV# are asserted. WE# and RST# must already have been deasserted. ADV# is asserted, and
then deasserted to latch the address. Alternately, ADV# can remain asserted throughout the burst
access, in which case the address is latched on the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the data buffer
on the next valid CLK edge after the initial access latency delay (see
Section 10.3.2, “Latency
Count” on page 55
). Subsequent data is output on valid CLK edges following a minimum delay.
相關PDF資料
PDF描述
PF48F2000P0ZTQ0 Intel StrataFlash Embedded Memory
PF48F3000P0ZTQ0 Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Pin; Insert Arrangement:10-6
PF48F4000P0ZTQ0 Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; Number of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle
PF48F0P0ZTQ0 Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:6; Connector Shell Size:10; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket; Insert Arrangement:10-98
PF48F2P0ZTQ0 Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT00; No. of Contacts:10; Connector Shell Size:12; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle
相關代理商/技術參數(shù)
參數(shù)描述
PF48F4400P0VBQ0A 功能描述:IC FLASH 512MBIT 85NS 88TPBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 產品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
PF48F4400P0VBQ2E 制造商:Micron Technology Inc 功能描述:32MX16 NOR FLASH PLASTIC PBF TFBGA 1.8V - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 512MBIT 85NS TFBGA
PF48F4400P0VBQ2F 制造商:Micron Technology Inc 功能描述:32MX16 NOR FLASH PLASTIC PBF TFBGA 1.8V - Tape and Reel
PF48F4400P0VBQE0 功能描述:IC FLASH 512MBIT 100NS 88SCSP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
PF48F4400P0VBQE3 功能描述:IC FLASH 512MBIT 100NS 88SCSP RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:Axcell™ 標準包裝:576 系列:- 格式 - 存儲器:閃存 存儲器類型:閃存 - NAND 存儲容量:512M（64M x 8） 速度:- 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應商設備封裝:48-TSOP 包裝:托盤 其它名稱:497-5040
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*