參數(shù)資料
型號： PF48F4400P0VBQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝： 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù)： 42/102頁
文件大?。?/td> 1609K
代理商： PF48F4400P0VBQ0
1-Gbit P30 Family
April 2005
42
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
W14
t
WHGL
WE# high to OE# low
0
-
ns
1,2,9
W16
t
WHQV
WE# high to read valid
t
AVQV
+ 35
-
ns
1,2,3,6,1
0
Write to Asynchronous Read Specifications
W18
t
WHAV
WE# high to Address valid
0
-
ns
1,2,3,6,8
Write to Synchronous Read Specifications
W19
t
WHCH/L
WE# high to Clock valid
19
-
ns
1,2,3,6,1
0
W20
t
WHVH
WE# high to ADV# high
19
-
ns
Write Specifications with Clock Active
W21
t
VHWL
ADV# high to WE# low
-
20
ns
1,2,3,11
W22
t
CHWL
Clock high to WE# low
-
20
ns
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
WLWH
or t
ELEH
) is defined from CE# or WE# low (whichever occurs last) to
CE# or WE# high (whichever occurs first). Hence, t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
Write pulse width high (t
WHWL
or t
EHEL
) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
).
t
WHVH
or t
must be met when transitioning from a write cycle to a synchronous burst read.
V
PP
and WP#
should be at a valid level until erase or program success is determined.
This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is
20 ns.
Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent
read operation to reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
5.
6.
7.
8.
9.
10.
11.
Table 18.
AC Write Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Units
Notes
Figure 22.
Write-to-Write Timing
W1
W7
W4
W7
W4
W3
W9
W3
W6
W2
W6
W2
W8
W8
W5
W5
Address [A]
CE# [E}
WE# [W]
OE# [G]
Data [D/Q]
RST# [P]
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