參數(shù)資料
型號： PF48F4400P0VBQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 32M X 16 FLASH 1.8V PROM, 88 ns, PBGA88
封裝： 8 X 11 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù)： 36/102頁
文件大小： 1609K
代理商： PF48F4400P0VBQ0
1-Gbit P30 Family
April 2005
36
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
R305
t
CHQX
Output hold from CLK
3
-
ns
1,5
R306
t
CHAX
Address hold from CLK
10
-
ns
1,4,5
R307
t
CHTV
CLK to WAIT valid
-
20
ns
1,5
R311
t
CHVL
CLK Valid to ADV# Setup
3
-
ns
1
R312
t
CHTX
WAIT Hold from CLK
3
-
ns
1,5
NOTES:
1.
See
Figure 13, “AC Input/Output Reference Waveform” on page 33
for timing measurements and max allowable input
slew rate.
OE# may be delayed by up to t
ELQV
– t
GLQV
after CE#’s falling edge without impact to t
ELQV
.
Sampled, not 100% tested.
Address hold in synchronous burst mode is t
or t
VHAX
, whichever timing specification is satisfied first.
Applies only to subsequent synchronous reads.
See your local Intel representative for designs requiring higher than 40 MHz synchronous operation.
2.
3.
4.
5.
6.
Table 16.
AC Read Specifications for 64/128-Mbit Densities (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Table 17.
AC Read Specifications for 256/512-Mbit and 1-Gbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Speed
Min
Max
Unit
Notes
Asynchronous Specifications
R1
t
AVAV
Read cycle time
Vcc = 1.8 V
– 2.0 V
85
-
ns
Vcc = 1.7 V
– 2.0 V
88
-
R2
t
AVQV
Address to output valid
Vcc = 1.8 V
– 2.0 V
-
85
ns
Vcc = 1.7 V
– 2.0 V
-
88
R3
t
ELQV
CE# low to output valid
Vcc = 1.8 V
– 2.0 V
-
85
ns
Vcc = 1.7 V
– 2.0 V
-
88
R4
t
GLQV
OE# low to output valid
-
25
ns
1,2
R5
t
PHQV
RST# high to output valid
-
150
ns
1
R6
t
ELQX
CE# low to output in low-Z
0
-
ns
1,3
R7
t
GLQX
OE# low to output in low-Z
0
-
ns
1,2,3
R8
t
EHQZ
CE# high to output in high-Z
-
24
ns
1,3
R9
t
GHQZ
OE# high to output in high-Z
-
24
ns
R10
t
OH
Output hold from first occurring address, CE#, or OE# change
0
-
ns
R11
t
EHEL
CE# pulse width high
20
-
ns
1
R12
t
ELTV
CE# low to WAIT valid
-
17
ns
R13
t
EHTZ
CE# high to WAIT high-Z
-
20
ns
1,3
R15
t
GLTV
OE# low to WAIT valid
-
17
ns
1
R16
t
GLTX
OE# low to WAIT in low-Z
0
-
ns
1,3
R17
t
GHTZ
OE# high to WAIT in high-Z
-
20
ns
Latching Specifications
相關(guān)PDF資料
PDF描述
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