參數(shù)資料
型號： PF48F2000P0ZBQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù)： 98/102頁
文件大?。?/td> 1609K
代理商： PF48F2000P0ZBQ0
1-Gbit P30 Family
April 2005
98
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
Table 38.
Protection Register Information
Table 39.
Burst Read Information
Offset
(1)
P = 10Ah
(P+E)h
Length
Description
Hex
Code
--02
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Add.
118:
Value
2
1
(P+F)h
(P+10)h
(P+11)h
(P+12)h
4
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
119:
11A:
11B:
11C:
--80
--00
--03
--03
80h
00h
8 byte
8 byte
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
10
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n”
∴
n = factory pgm'd groups (low byte)
11D:
11E:
11F:
120:
121:
122:
123:
124:
125:
126:
--89
--00
--00
--00
--00
--00
--00
--10
--00
--04
89h
00h
00h
00h
0
0
0
16
0
16
bits 40–47 = “n”
∴
n = factory pgm'd groups (high byte)
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n”
∴
n = user pgm'd groups (low byte)
bits 64–71 = “n”
∴
n = user pgm'd groups (high byte)
bits 72–79 = “n”
∴
2
n
= user programmable bytes/group
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2
n
= factory pre-programmed bytes
bits 24–31 = “n” such that 2
n
= user programmable bytes
Offset
(1)
P = 10Ah
(P+1D)h
Length
Description
Hex
Code
--03
(Optional flash features and commands)
Page Mode Read capability
bits 0–7 = “n” such that 2
n
HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2
n+1
HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data output width.
Add.
127:
Value
8 byte
1
(P+1E)h
1
128:
--04
4
(P+1F)h
1
129:
--01
4
(P+20)h
(P+21)h
(P+22)h
1
1
1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
12A:
12B:
12C:
--02
--03
--07
8
16
Cont
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