參數(shù)資料
型號: PF48F2000P0ZBQ0
廠商: INTEL CORP
元件分類: PROM
英文描述: Intel StrataFlash Embedded Memory
中文描述: 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝: 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數(shù): 35/102頁
文件大小: 1609K
代理商: PF48F2000P0ZBQ0
1-Gbit P30 Family
Datasheet
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
35
7.3
AC Read Specifications
Table 16.
AC Read Specifications for 64/128-Mbit Densities (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Notes
Asynchronous Specifications
R1
t
AVAV
t
AVQV
Read cycle time
85
-
ns
R2
Address to output valid
-
85
ns
R3
t
ELQV
CE# low to output valid
-
85
ns
R4
t
GLQV
OE# low to output valid
-
25
ns
1,2
R5
t
PHQV
RST# high to output valid
-
150
ns
1
R6
t
ELQX
CE# low to output in low-Z
0
-
ns
1,3
R7
t
GLQX
OE# low to output in low-Z
0
-
ns
1,2,3
R8
t
EHQZ
CE# high to output in high-Z
-
24
ns
1,3
R9
t
GHQZ
OE# high to output in high-Z
-
24
ns
R10
t
OH
Output hold from first occurring address, CE#, or OE# change
0
-
ns
R11
t
EHEL
CE# pulse width high
20
-
ns
1
R12
t
ELTV
CE# low to WAIT valid
-
17
ns
R13
t
EHTZ
CE# high to WAIT high-Z
-
20
ns
1,3
R15
t
GLTV
OE# low to WAIT valid
-
17
ns
1
R16
t
GLTX
OE# low to WAIT in low-Z
0
-
ns
1,3
R17
t
GHTZ
OE# high to WAIT in high-Z
-
20
ns
Latching Specifications
R101
t
AVVH
Address setup to ADV# high
10
-
ns
1
R102
t
ELVH
CE# low to ADV# high
10
-
ns
R103
t
VLQV
ADV# low to output valid
-
85
ns
R104
t
VLVH
ADV# pulse width low
10
-
ns
R105
t
VHVL
ADV# pulse width high
10
-
ns
R106
t
VHAX
Address hold from ADV# high
9
-
ns
1,4
R108
t
APA
Page address access
-
25
ns
1
R111
t
phvh
RST# high to ADV# high
30
-
ns
Clock Specifications
R200
f
CLK
CLK frequency
-
40
MHz
1,3,6
R201
t
CLK
CLK period
25
-
ns
R202
t
CH/CL
CLK high/low time
5
-
ns
R203
t
FCLK/RCLK
CLK fall/rise time
-
3
ns
Synchronous Specifications
R301
t
AVCH/L
Address setup to CLK
9
-
ns
1
R302
t
VLCH/L
ADV# low setup to CLK
9
-
ns
R303
t
ELCH/L
CE# low setup to CLK
9
-
ns
R304
t
CHQV
/ t
CLQV
CLK to output valid
-
20
ns
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