參數資料
型號： PF48F2000P0ZBQ0
廠商： INTEL CORP
元件分類： PROM
英文描述： Intel StrataFlash Embedded Memory
中文描述： 4M X 16 FLASH 1.8V PROM, 85 ns, PBGA88
封裝： 8 X 10 MM, 1.20 MM HEIGHT, LEAD FREE, SCSP-88
文件頁數： 88/102頁
文件大小： 1609K
代理商： PF48F2000P0ZBQ0
1-Gbit P30 Family
April 2005
88
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
Figure 43.
BEFP Flowchart
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing).
BEFP Exit
Repeat for subsequent blocks;
After BEFP exit, a full Status Register check can
determine if any program error occurred;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state.
Standby
Read
Bus
State
Operation
Status
Register
Check
Exit
Status
Comments
Data = Status Register Data
Address = 1
Word Addr.
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
BEFP Setup
Comments
Bus
State
Operation
Write
(Note 1)
BEFP
Setup
Write
BEFP
Confirm
Read
Status
Register
Standby
BEFP
Setup
Done
Write
Unlock
Block
Data = 0x80 @ 1
st
Word
Address
Data = 0x80 @ 1
st
Word
Address
Data = Status Register Data
Address = 1
Word Addr.
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
V
PPH
applied to VPP
Standby
Error
Condition
Check
If SR[7] is set, check:
SR[3] set = V
PP
Error
SR[1] set = Locked Block
No (SR[0]=1)
Write Data @ 1
st
Word Address
Last
Data
Write 0xFFFF,
Address Not within
Current Block
Program
Done
Read
Status Reg.
Yes (SR[0]=0)
Y
No (SR[7]=0)
Full Status Check
Procedure
Program
Complete
Read
Status Reg.
BEFP
Exited
Yes (SR[7]=1)
Start
Write 80h @
1
st
Word Address
V
applied
Block Unlocked
Write D0h @
1
st
Word Address
BEFP Setup
Done
Read
Status Reg.
No (SR[7]=1)
Exit
N
Program & Verify Phase
Exit Phase
Setup Phase
BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE
Check
X = 32
Initialize Count:
X = 0
Increment Count:
X = X+1
Y
N
Check V
PP
, Lock
errors (SR[3,1])
Yes (SR[7]=0)
BEFP Setup delay
Data Stream
Ready
Read
Status Reg.
Yes (SR[0]=0)
No (SR[0]=1)
BEFP Program & Verify
Comments
Bus
State
Write
(note 2)
Load
Buffer
Standby
Increment
Count
Standby
Initialize
Count
Data = Data to Program
Address = 1
st
Word Addr.
X = X+1
X = 0
Read
Status
Register
Standby
Program
Done
Data = Status Reg. Data
Address = 1
Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
Write
Exit Prog &
Verify Phase
Data = 0xFFFF @ address
not in current block
Standby
Last
Data
No = Fill buffer again
Yes = Exit
Standby
Buffer
Full
X = 32
Yes = Read SR[0]
No = Load Next Data Word
Read
Standby
Status
Register
Data Stream
Ready
Data = Status Register Data
Address = 1
Word Addr.
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Operation
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PF48F2000P0ZBQ0A 功能描述:IC FLASH 64MBIT 85NS 88TPBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 產品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ
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