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參數(shù)資料
| 型號： | PF48F0P0ZBQ0 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 英特爾StrataFlash嵌入式存儲器 |
| 文件頁數(shù)： | 42/102頁 |
| 文件大小： | 1609K |
| 代理商： | PF48F0P0ZBQ0 |
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1-Gbit P30 Family
April 2005
42
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
W14
t
WHGL
WE# high to OE# low
0
-
ns
1,2,9
W16
t
WHQV
WE# high to read valid
t
AVQV
+ 35
-
ns
1,2,3,6,1
0
Write to Asynchronous Read Specifications
W18
t
WHAV
WE# high to Address valid
0
-
ns
1,2,3,6,8
Write to Synchronous Read Specifications
W19
t
WHCH/L
WE# high to Clock valid
19
-
ns
1,2,3,6,1
0
W20
t
WHVH
WE# high to ADV# high
19
-
ns
Write Specifications with Clock Active
W21
t
VHWL
ADV# high to WE# low
-
20
ns
1,2,3,11
W22
t
CHWL
Clock high to WE# low
-
20
ns
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
WLWH
or t
ELEH
) is defined from CE# or WE# low (whichever occurs last) to
CE# or WE# high (whichever occurs first). Hence, t
WLWH
= t
ELEH
= t
WLEH
= t
ELWH
.
Write pulse width high (t
WHWL
or t
EHEL
) is defined from CE# or WE# high (whichever occurs first) to
CE# or WE# low (whichever occurs last). Hence, t
WHWL
= t
EHEL
= t
WHEL
= t
EHWL
).
t
WHVH
or t
must be met when transitioning from a write cycle to a synchronous burst read.
V
PP
and WP#
should be at a valid level until erase or program success is determined.
This specification is only applicable when transitioning from a write cycle to an asynchronous read.
See spec W19 and W20 for synchronous read.
When doing a Read Status operation following any command that alters the Status Register, W14 is
20 ns.
Add 10 ns if the write operations results in a RCR or block lock status change, for the subsequent
read operation to reflect this change.
These specs are required only when the device is in a synchronous mode and clock is active during
address setup phase.
5.
6.
7.
8.
9.
10.
11.
Table 18.
AC Write Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Min
Max
Units
Notes
Figure 22.
Write-to-Write Timing
W1
W7
W4
W7
W4
W3
W9
W3
W6
W2
W6
W2
W8
W8
W5
W5
Address [A]
CE# [E}
WE# [W]
OE# [G]
Data [D/Q]
RST# [P]
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PF48F0P0ZT00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F0P0ZTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F2000P0ZBQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F2000P0ZBQ0A | 功能描述:IC FLASH 64MBIT 85NS 88TPBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
| PF48F2000P0ZTQ0 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx StrataFlash Embedded Memory |
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