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參數(shù)資料
| 型號： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁數(shù)： | 6/99頁 |
| 文件大小： | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
14
Order Number: 313295-002US
4.1
Signal Descriptions
Table 2.
Signal Descriptions (Sheet 1 of 3)
Symbol Type
Signal Descriptions
Notes
Address and Data Signals, AD-Mux
A[MAX:16]
Input
ADDRESS:
Global device signals.
Shared address inputs for all memory die during Read and Write operations.
256-Mbit: AMAX = A23
128-Mbit: AMAX = A22
64-Mbit: AMAX = A21
A0 is the lowest-order word address.
Unused address inputs should be treated as RFU.
DQ[15:0]
Input /
Output
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS:
AD-Mux I/O flash signals.
During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data
output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by
commands or data.
DQ[15:0] are High-Z when the device is deselected or its output is disabled.
DQ[15:0] is only used with AD-Mux I/O flash device.
1
Control Signals
ADV#
Input
ADDRESS VALID:
Flash- and Synchronous PSRAM-specific signal; low-true input.
During a synchronous flash Read operation, the address is latched on the rising edge of ADV#
or the first active CLK edge whichever occurs first. In an asynchronous flash Read operation,
the address is latched on the rising edge of ADV# or continuously flows through while ADV# is
low.
During synchronous PSRAM read and synchronous write modes, the address is either latched
on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever
edge comes first. In asynchronous read and asynchronous write modes, ADV# can be used to
latch the address, but can be held low for the entire operation as well.
Note:
During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase.
F[3:1]-CE#
Input
FLASH CHIP ENABLE:
Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs
are placed in a High-Z state.
F1-CE# is dedicated to flash die #1.
F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any
unused flash chip enable should be treated as RFU.
CLK
Input
CLOCK:
Flash- and Synchronous PSRAM-specific input signal.
CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous
operations.
F[2:1]-OE#
Input
FLASH OUTPUT ENABLE:
Flash-specific signal; low-true input.
When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables
the output drivers of the selected flash die and places the output drivers in High-Z.
F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly
recommended to always common F1-OE# and F2-OE# on the PCB.
R-OE#
Input
RAM OUTPUT ENABLE:
PSRAM- and SRAM-specific signal; low-true input.
When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#
disables the output drivers of the selected memory die and places the output drivers in High-Z. If
device not present, treat as RFU.
2
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