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參數(shù)資料
| 型號： | PF38F40L0YUQ0 |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 1.8V PROM, PBGA88 |
| 封裝： | 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88 |
| 文件頁數(shù)： | 1/99頁 |
| 文件大?。?/td> | 1419K |
| 代理商： | PF38F40L0YUQ0 |
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Order Number: 313295-002US
July 2006
Intel StrataFlash Wireless Memory (L18)
with A/D-Multiplexed I/O
Datasheet
Product Features
High performance Read-While-Write/Erase
— 85 ns initial access
— 54MHz with zero wait state, 14 ns clock-to-
data output synchronous-burst mode
— 4-, 8-, 16-, and continuous-word burst mode
— Burst suspend
— Programmable WAIT configuration
— Buffered Enhanced Factory Programming
(Buffered EFP): 5 s/byte (Typ)
— 1.8 V low-power buffered and non-buffered
programming @ 7 s/byte (Typ)
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Multiple 16-Mbit partitions: 256Mb devices
— Four 16-KWord parameter blocks: top
configuration
— 64-KWord main blocks
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Status register for partition and device status
Power
— 1.7 V to 2.0 V VCC operation
— I/O voltage: 1.35 V – 2.0 V, 1.7 V– 2.0 V
— Standby current: 25 A (Typ) for 256-Mbit
— 4-Word synchronous read current: 15 mA
(Typ) @ 54 MHz
— Automatic Power Savings (APS) mode
Security
— OTP space:
64 unique device identifier bits
64 user-programmable OTP bits
Additional 2048 user-programmable OTP bits
— Absolute write protection: VPP = GND
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Software
— 20 s (Typ) program suspend
— 20 s (Typ) erase suspend
— Intel Flash Data Integrator (FDI) optimized
— Basic Command Set (BCS) and Extended
Command Set (ECS) compatible
— Common Flash Interface (CFI) capable
Quality and Reliability
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— ETOX VIII process technology (0.13 m)
Density and Packaging
— 64-, 128-, and 256 Mbit density in VF BGA
package
— 16-bit wide data bus
The Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O product is the latest generation of
Intel StrataFlash memory featuring flexible, multiple-partition, dual operation. It provides high performance
asynchronous read mode and synchronous-burst read mode using 1.8 V low-voltage, multi-level cell (MLC)
technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background. 8-Mbit partitions allow system designers to choose the size of the code and data segments.
The Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O device is manufactured using Intel
0.13 m ETOX VIII process technology, available in industry-standard chip scale packaging.
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