參數(shù)資料
型號(hào)： PF38F40L0YUQ0
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, PBGA88
封裝： 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件頁數(shù)： 16/99頁
文件大?。?/td> 1419K
代理商： PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
23
Intel StrataFlash Wireless Memory (L18)
7.2
Capacitance
7.3
AC Read Specifications (V
CCQ
= 1.35 V – 2.0 V)
Table 6.
Capacitance
Symbol
Parameter
Signals
Min Typ Max Unit
Condition
Note
CIN
Input Capacitance
Address, CE#,
WE#, OE#, RST#,
CLK, ADV#, WP#
26
7
pF Typ temp= 25 °C,
Max temp = 85 °C,
VCC=VCCQ=(0-1.95)
V, Silicon die
1,2
COUT
Output Capacitance Data, WAIT
2
4
5
pF
Notes:
1.
Sampled, not 100% tested.
2.
Silicon die capacitance only, add 1 pF for discrete packages.
Table 7.
AC Read Specifications (V
CCQ
= 1.35 V – 2.0 V)
Num Symbol
Parameter
All
Densities
Speed
-90
Unit
s
Notes
Min Max
Asynchronous Specifications
R1
t
AVAV
Read cycle time
90
ns
1,6
R2
tAVQV
Address to output valid
90
ns
R3
t
ELQV
CE# low to output valid
90
ns
R4
t
GLQV
OE# low to output valid
25
ns
1,2
R5
t
PHQV
RST# high to output valid
150
ns
1
R6
t
ELQX
CE# low to output in low-Z
0
ns
1,3
R7
t
GLQX
OE# low to output in low-Z
0
ns
1,2,3
R8
t
EHQZ
CE# high to output in high-Z
20
ns
1,3
R9
t
GHQZ
OE# high to output in high-Z
20
ns
R10 t
OH
Output hold from first occurring address, CE#, or OE#
change
0ns
R11 t
EHEL
CE# pulse width high
17
ns
1
R12 t
ELTV
CE# low to WAIT valid
17
ns
1
R13 t
EHTZ
CE# high to WAIT high Z
17
ns
1,3
R14 t
GHTV
OE# high to WAIT Valid
17
ns
R15 t
GLTV
OE# low to WAIT Valid
17
ns
Latching Specifications
R101 t
AVVH
Address setup to ADV# high
7
ns
1
R102 t
ELVH
CE# low to ADV# high
10
ns
R103 t
VLQV
ADV# low to output valid
90
ns
R104 t
VLVH
ADV# pulse width low
7
ns
R105 t
VHVL
ADV# pulse width high
7
ns
R106 t
VHAX
Address hold from ADV# high
7
ns
1,4
R107 t
VHGL
ADV# high to OE# low
7
ns
1
R111 tPHVH
RST# high to ADV# high
30
ns
1
Clock Specifications
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