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參數(shù)資料
| 型號： | PDI1394L21BP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1394 full duplex AV link layer controller |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, PLASTIC, SOT-386-1, TQFP-100 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394L21BP |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
5
5.0
PIN DESCRIPTION
Name
Pin Type
LQFP
Pin
Numbers
LFBGA
Ball
Numbers
I/O
Description
AGND
Supply
32, 33,
39, 48,
49, 50
A1, A5,
A8, B1,
B2, B7
—
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
AV
DD
Supply
30, 31,
42, 51,
52
B8, C2,
C3, C5,
C7, D2
—
Analog circuit power terminals. A combination of high frequency
decoupling capacitors on each side are suggested, such as paralleled
0.1
μ
F and 0.001
μ
F. These supply terminals are separated from
PLLV
and DV
internal to the device to provide noise isolation. They
should be tied at a low impedance point on the circuit board.
BRIDGE
CMOS
28
D6
I
BRIDGE input. This input is used to set the Bridge_Aware bits located in
the Vendor-Dependent register Page 7, base address 1001
b
, bit
positions 6 and 7. This pin is sampled during a hardware reset (RESET
low). When the BRIDGE pin is tied low (or through a 1 k
resistor to
accommodate other vendor’s pin-compatible chips), the Bridge_Aware
bits are set to “00” indicating a “non-bridge device.” When the BRIDGE
pin is tied high, the Bridge_Aware bits are set to “11” indicating a “1394.1
bridge compliant” device. The default setting of the Bridge_Aware bits
can be overridden by writing to the register. The Bridge_Aware bits are
reported in the self-ID packet at bit positions 18 and 19.
C/LKON
CMOS 5V tol
19
F6
I/O
Bus Manager/Isochronous Resource Manager (IRM) Contender
programming input and link-on output. On hardware reset, this terminal
is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-k
resistor to a high (contender) or low (not contender). The resistor allows
the link-on output to override the input.
If this pin is connected to a LLC driver pin for setting Bus Manager/IRM
contender status, then a 10-k
series resistor should be placed on this
line between the PHY and the LLC to prevent possible contention. In this
case. the pull-high or pull-low resistors mentioned in the previous
paragraph should not be used. Refer to Figure 9.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is otherwise driven low,
except during hardware reset when it is high impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the
LCtrl bit cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node,
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-timeout interrupt), CPSI
(cable-power-status interrupt), or STOI (state-timeout interrupt)
register bits are 1 and the RPIE (resuming-port interrupt enable)
register bit is also 1.
Once activated, the link-on output will continue active until the LLC
becomes active (both LPS active and the LCtrl bit set). The PHY also
deasserts the link-on output when a bus-reset occurs unless the link-on
output would otherwise be active because one of the interrupt bits is set
(i.e., the link-on output is active due solely to the reception of a link-on
PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the
link-on output to be activated if the LLC were inactive, the link-on output
will be activated when the LLC subsequently becomes inactive.
CNA
CMOS
3
F3
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
CPS
CMOS
24
E5
I
Cable Power Status input. This terminal is normally connected to cable
power through a 390 k
resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
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PDF描述 |
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| PDL-TTL-7-15 | Programmable Delay Line |
| PDL-TTL-7-2 | Programmable Delay Line |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| PDI1394L40BE,551 | 制造商:NXP Semiconductors 功能描述:1394 A/V LINK LAYER - Trays |
| PDI1394L40BE,557 | 功能描述:視頻 IC DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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