- 您現在的位置：買賣IC網 > PDF目錄369960 > PDI1394L21BP (NXP SEMICONDUCTORS) 1394 full duplex AV link layer controller PDF資料下載
參數資料
| 型號： | PDI1394L21BP |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1394 full duplex AV link layer controller |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1 MM HEIGHT, PLASTIC, SOT-386-1, TQFP-100 |
| 文件頁數： | 19/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394L21BP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
19
Table 8. Page 7 (Vendor-Dependent) Register Field Descriptions
FIELD
SIZE
2
TYPE
Rd/Wr
DESCRIPTION
Link_Speed
Link speed. This field indicates the top speed capability of the attached LLC. Encoding is as follows:
Code
Speed
00
S100
01
S200
10
S400
11
illegal
This field is replicated in the “sp” field of the self-ID packet to indicate the speed capability of the node
(PHY and LLC in combination). However, this field does not affect the PHY speed capability indicated to
peer PHYs during self-ID; the PDI1394P23 PHY identifies itself as S400 capable to its peers regardless
of the value in this field. This field is set to 10b (S400) by hardware reset and is unaffected by bus-reset.
An 11b can be written into this field, however, a 10b will be sent in the self-ID packet.
Bridge_Aware
2
Rd/Wr
Bridge_Aware. This field reports Bridge_Aware capability to all nodes via the self-ID packet. Encoding
is as follows:
Code
Meaning
00
Non-bridge device
01
Reserved (BRAN Bridge)
10
Bridge compliant with 1394.1 (unchanged state)
11
Bridge compliant with 1394.1 (changed state)
This field is replicated in bits 18 and 19 of the self-ID packet. The value of this field does not affect PHY
operation. It is a reporting mechanism. The default value for this field is set by the BRIDGE pin. The
BRIDGE pin is sampled during a hardware reset (RESET low). When the BRIDGE pin is low, this field
is set to “00” indicating a “non-bridge device.” When the BRIDGE pin is high, this field is set to “11”
indicating a “1394.1 bridge compliant” device. Writing to this field overrides the default setting by the
BRIDGE pin.
相關PDF資料 |
PDF描述 |
|---|---|
| PDL-TTL-7-1 | Programmable Delay Line |
| PDL-TTL-7-14 | Programmable Delay Line |
| PDL-TTL-7-15 | Programmable Delay Line |
| PDL-TTL-7-2 | Programmable Delay Line |
| PDL-TTL-7-20 | Programmable Delay Line |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| PDI1394L40BE,551 | 制造商:NXP Semiconductors 功能描述:1394 A/V LINK LAYER - Trays |
| PDI1394L40BE,557 | 功能描述:視頻 IC DO NOT USE ORDER -S OR -T PART RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。