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參數(shù)資料
| 型號(hào)： | PCI2050PDV |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線控制器 |
| 文件頁(yè)數(shù)： | 7/17頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050PDV |
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PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
7
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
secondary PCI interface control terminals
TERMINAL
NAME
I/O
DESCRIPTION
NO.
S_IRDY
177
I/O
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the current
data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and
S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_LOCK
172
I/O
Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as a master.
S_PAR
168
I/O
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across the S_AD
and S_C/BE buses. As a master during PCI write cycles, the bridge outputs this parity indicator with a
one-S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the master parity
indicator. A miscompare can result in a parity error assertion (S_PERR).
S_PERR
171
I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that calculated
parity does not match S_PAR when enabled through the command register (PCI offset 04h).
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
9
8
7
6
5
4
3
2
207
I
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used as
inputs from secondary PCI bus masters requesting the bus. Ten potential masters (including the bridge) can
be located on the secondary PCI bus.
When the internal arbiter is disabled, the S_REQ0 signal is reconfigured as an external secondary bus grant
for the bridge.
S_SERR
169
I
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled through the
bridge control register (PCI offset 3Eh). S_SERR is never asserted by the bridge.
S_STOP
173
I/O
Secondary cycle stop signal. S_STOP is driven by a PCI target to request that the master stop the current
secondary bus transaction. S_STOP is used for target disconnects and is commonly asserted by target devices
that do not support burst data transfers.
S_TRDY
176
I/O
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY and
S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
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