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參數(shù)資料
| 型號(hào)： | PCI2050PDV |
| 英文描述： | BUS CONTROLLER |
| 中文描述： | 總線(xiàn)控制器 |
| 文件頁(yè)數(shù)： | 5/17頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | PCI2050PDV |
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PCI2050A
PCI-to-PCI BRIDGE
SCPS067
–
MAY 2001
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
secondary PCI system terminals
TERMINAL
NAME
I/O
DESCRIPTION
NO.
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
42
41
39
38
36
35
33
32
30
29
O
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each secondary
bus device samples all secondary PCI signals at the rising edge of its corresponding S_CLKOUT input.
S_CLK
21
I
Secondary PCI bus clock input. This input synchronizes the PCI2050 to the secondary bus clocks.
S_CFN
23
I
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled. When
the external arbiter is enabled, the PCI2050 S_REQ0 terminal is reconfigured as a secondary bus grant input
to the bridge and S_GNT0 is reconfigured as a secondary bus master request to the external arbiter on the
secondary bus.
S_RST
22
O
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit (bit 6)
of the bridge control register (PCI offset 3Eh). S_RST is asynchronous with respect to the state of the
secondary interface CLK signal.
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